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Asynchronous Counter Design - Pls Advise...

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student2005

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I refer to reference books like Tocci, Kleitz, and Floyd, but could not find an example that shows how to design an asynchronous counter.

I wish to design an asynchronous counter that repeat the following sequence:
0 -> 2 -> 4 -> 3 -> 7 -> 6 -> 0...

Positive-triggered JK FF should be used to implement the counter.

Please advise.

Many thanks.
 
If you search my posts, you will find that I did a counter design for someone a year or 2 ago. It should help you with this one.
 
ljcox said:
If you search my posts, you will find that I did a counter design for someone a year or 2 ago. It should help you with this one.
I searched for 'ljcox' and 'counter', but no result. Possible to give me the link? Thanks in advance.
 
ljcox said:
If you search my posts, you will find that I did a counter design for someone a year or 2 ago. It should help you with this one.
I could not find an example even after I read many ref books in library. Pls help me in the async counter design. Thanks.
 
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that is not a counter you want. a counter count 0-max number without skipping any. what u need is a counter that counts the amount of figures u want in total ie:
0 -> 2 -> 4 -> 3 -> 7 -> 6 -> 0
needs 6 states. u then feed the numbers 0-5 to a logic circuit that for each input number will give the required output number.
an ordinary counter will not do what u are asking unless the word counter has changed meaning sine i studied them 2 weeks ago
 
Thunderchild said:
what u need is a counter that counts the amount of figures u want in total ie:
0 -> 2 -> 4 -> 3 -> 7 -> 6 -> 0
needs 6 states. u then feed the numbers 0-5 to a logic circuit that for each input number will give the required output number.
This is not necessary. It is possible to design a counter to count in the required pattern without the need for converting logic.

For example, see https://www.electro-tech-online.com/threads/ups-circuit.7854/
 
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well by the time all the various gates are added and it is worked out (not an easy task - for me anyhow) won't my suggestion be faster with the same amount of circuitry ?
 
Thunderchild said:
well by the time all the various gates are added and it is worked out (not an easy task - for me anyhow) won't my suggestion be faster with the same amount of circuitry ?
Yes it may be quicker, but that is beside the point. I would have thought that you need the experience of designing a state machine.

Besides, I expect you will need more gates to do it that way. The objective of electronic design is to produce a workable design with a minimum of hardware, ie. minimum cost.
 
yes true. unfortunately i'm not that good in dealing with flip flops in this way. when i finally manage to get a bread board i'll be able to experiment a bit
 
Hey, Student2005 .... how about some more information here just to satisfy my curiosity (since I've been an electronics teacher for 23+ years now) .... is this just something that you want to do just for kicks (which is OK) or do you have a demented teacher who's dumping some weirdo crap on you for a project before he/she even teaches you about synchronous counters, altering modulos, stopping on-count, presetting, resetting, etc. In other words, is there an ultimate point to this weird "count" sequence? It's far more practical for a project to design a counter for a 12-hour clock from standard TTL or CMOS logic -- not as easy as one first assumes.

Dean
 
Dean Huster said:
Hey, Student2005 .... how about some more information here just to satisfy my curiosity (since I've been an electronics teacher for 23+ years now) .... is this just something that you want to do just for kicks (which is OK) or do you have a demented teacher who's dumping some weirdo crap on you for a project before he/she even teaches you about synchronous counters, altering modulos, stopping on-count, presetting, resetting, etc. In other words, is there an ultimate point to this weird "count" sequence? It's far more practical for a project to design a counter for a 12-hour clock from standard TTL or CMOS logic -- not as easy as one first assumes.
Well... It's a past question from a university. Do you have any idea? In my opinion, it's not easy. Am I right? Thanks.
 
student2005 said:
Well... It's a past question from a university. Do you have any idea? In my opinion, it's not easy. Am I right? Thanks.
It is not very difficult. You make a "next state" diagram as I did in one of the examples I gave you the URL of above and then produce the Karnough maps of the J & K inputs.
There is no point in us doing it for you otherwise you won't learn.
 
ljcox said:
student2005 said:
Well... It's a past question from a university. Do you have any idea? In my opinion, it's not easy. Am I right? Thanks.
It is not very difficult. You make a "next state" diagram as I did in one of the examples I gave you the URL of above and then produce the Karnough maps of the J & K inputs.
There is no point in us doing it for you otherwise you won't learn.
In your case, what's the input to the positive-edge-triggered of each flip-flop? Thanks.
 
student2005 said:
In your case, what's the input to the positive-edge-triggered of each flip-flop? Thanks.
Im afraid that I don't understand your question. Please elaborate.
 
ljcox said:
student2005 said:
In your case, what's the input to the positive-edge-triggered of each flip-flop? Thanks.
Im afraid that I don't understand your question. Please elaborate.
For synchronous counter design, we know each FF is connected to the same clock source. For asynchronous counter design, e.g. the output of first FF is connected to the clock input of the next FF. Therefore, in your design, what's the input to the positive-edge-triggered of each FF? Thanks.
 
I have thought about the asynchronous counter and I have concluded that it would be better to do it as a synchronous counter. In order to do it as an asychronous counter, the Ck inputs to each FF would need to be gated with one or more outputs of the FFs and the clock signal.

This is because in some cases, the only signal that changes is the clock. For example, from state 7 to 6, FFa has to go from 1 to 0, but FFb and FFc do not change.
 
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