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OK.I am clocking externally, so I've got SCK=0 at the fall of CS_n.
No need to clock SCK to check for EOC_n. However you have to bring CS_n -> 0, for EOC_n to assert it's state (of course while keeping SCK low).As long and thorough as it appears, I still find Linear's spec very confusing. I assume the way to detect EOC_n is to put a pullup resistor on SDO and wait for it to fall low?
Does the part need to be clocked for the EOC_n to assert, or does it fall on its own?
Yes.After CS_n=0, doesn't the part do an automatic conversion on CH0? So I wait for EOC_n so I can clock out this junk and clock in the desired conversion into SDI?
Does the 2418 HAVE to clock in the SDI at the same time as the data clocks out, or can you hold SDI high and use the 1->0 transition to indicate the start of the request?
Oznog said:Is it necessary to do a CS_N=1 between giving the conversion request and awaiting the result?
Oznog said:Here's my current implementation:
Init:
CS_N=1;SCK=0;SDI=1;
delay;
CS_N=1; <-- Is this correct?
}
Oznog said:Huh. Looking at the pin #defines in my C code, I did use the LB4, the latch value, for SDO. Now I've never been sure I fully understood the difference. I have an output value now.
I stripped the last 6 bits of channel & parity, and get these values:
Applying 5V gives 0xc00000. It's a totally static value with no noise. Since bit 23 is a sign bit indicating 'positive', it's 0x40000, or 262144.
Grounding the input gave 0x801AD1, the exact value changes every sample. Stripping the sign bit gives 0x001ad1, or 6865.
So the value from giving gnd is small and looks like it'd be zero if not for ground noise. But why is the value when applying 5V so far from the 0x7fffff I'd expect??? And why is it reading a totally static value? There should logically be some noise in it.