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anyone know why this signal is floating high? (picture)

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hi.
If I follow what your diagram shows, ie the gate pulse high from TX to RX, this enables the pulses from the 555 to input to the range counter.

Is this what you mean.?
 
yes!! enables the pulse counter

Usually a range finder sets a bistable at the transmission time and resets it when the received echo is detected.
The period of the gate is the time to and from the target.

The 555 pulse generator freq is chosen to give a gated count [ via the bistable] proportional to the range of the target.

Does this explain it OK.?
 
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Usually a range finder sets a bistable at the transmission time and resets it when the received echo is detected.
The period of the gate is the time to and from the target.

The 555 pulse generator freq is chosen to give a gated count [ via the bistable] proportional to the range of the target.

Does this explain it OK.?

yes i understand how the circuit works, just i thought when the range finder is inactive its output should be LOW.. but its not.. its just sitting high, so the pulsecounter is constantly counting when it shouldnt be
 
Why not use the Pulse out to control the 555 reset pin?

If you're not getting anything on pulse out how do you know the sonar is working?
 
What series AND gate is that? If it is a CMOS you need to ground the other inputs so they dont cause unwanted high speed internal switching.
 
yes i understand how the circuit works, just i thought when the range finder is inactive its output should be LOW.. but its not.. its just sitting high, so the pulsecounter is constantly counting when it shouldnt be
Well, if the output is normally high and goes low when an echo is received, then you should be using an OR gate instead of an AND gate. You should use a NOR gate instead if you want the inactive state of the pulse counter input to rest in the low state.
 
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Why not use the Pulse out to control the 555 reset pin?

If you're not getting anything on pulse out how do you know the sonar is working?

What series AND gate is that? If it is a CMOS you need to ground the other inputs so they dont cause unwanted high speed internal switching.

Well, if the output is normally high and goes low when an echo is received, then you should be using an OR gate instead of an AND gate. You should use a NOR gate instead if you want the inactive state of the pulse counter input to rest in the low state.

I think the echo out is normally low and pulses high.
SRF05 Technical Documentation

I wonder how the mode pin is connected?



thanks all for invaluable tips & help... I just threw in a NAND gate on a wing and a prayer and hey presto :p annoying when the documentation doesnt match up to the device itself!!


The SRf05 is left open for mode i think as well
 
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