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(Analog) Is this a D flip-flop?

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genxium

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This component is from the ADS 2008 example, I don't quite understand how it works clearly.

By far I think that if D=0,CLK=1 , then the collector current Ic of BJT1 is small, resulting in that Vc of BJT1 is High, hence Vb of BJT14 is High and BJT14 is active, so [LATEX]\bar{Q}[/LATEX]=1.

But I have no idea how to figure out Q when D=0, CLK=1, can anyone give me a hint?
 

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RCinFLA

Well-Known Member
Sort of. The second diff pair form the latch. 'Clk not' must stay high during idle to keep second diff amp latch going or it will go to undefined state.

There may be a race condition when transitioning allowing a momentary undefined state if the rise time is too slow or 'Clk not' releases slightly before D goes high.
 

genxium

New Member
Sort of. The second diff pair form the latch. 'Clk not' must stay high during idle to keep second diff amp latch going or it will go to undefined state.

There may be a race condition when transitioning allowing a momentary undefined state if the rise time is too slow or 'Clk not' releases slightly before D goes high.

Thank you so much for such a quick reply! ^_^

Can you help me with another question also about this figure? I wanna know if the left most 2 BJTs with collector resistor are working as inverters here(if 'CLK' is high)?
 

Roff

Well-Known Member
Q follows D when clock is high. When clock goes low, Q latches in current state. It's a D latch.
To make an edge-clocked D FF, you need two stages cascaded, with the clock inputs on the second (slave latch) inverted relative to master latch.
When clock is high, the voltages at the collectors of the input differential pair will indeed be the complements of their respective bases,
 
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