Am I missing something here? Huge startup time for boost converter?

[FusionITR]

https://www.electro-tech-online.com/custompdfs/2011/07/FAN7529.pdf

If you look at the application notes and the sample schematic, you will see that the startup bias is using a 330k resistor and 47uf cap with a internal zener clamp (22V). The startup voltage is 12V (typ) so the voltage would have to at least charge to 12V. Wouldn't this take forever (seconds) with huge bias resistor?

 

[ronv]

Looks like about a second since it is charging to the peak ac line voltage.

 

[FusionITR]

Looks like about a second since it is charging to the peak ac line voltage.

It's not charging to the peak line voltage because theres a 22V clamp. When it charges to 12V the pwm is suppose to wake up but even charging to 12V will take over a second according to those values.

So I guess my basic question is boost converters (or any offline design) are usually designed to take that long to start up?

 

[ronv]

I think this is the deal:
When it first starts the RC is the supply. Since it is powered from the ac line voltage the resistor has to be large to limit the zener current and the resistor wattage. The cap has to be that large to supply the run current. I think at lower input voltages the time constant could be much shorter.
Are you using it for a boost converter or power factor correction?
Google the App. note

 

[FusionITR]

Understood, so it's just accepted due to these contraints that the startup time will be 1 second+?

 

[ronv]

I think so. There is an app note on the calculations. Sorry I should have included it.
https://www.electro-tech-online.com/custompdfs/2011/07/AN-6026.pdf

 

[FusionITR]

Damn, nice find, thanks!

 

[FusionITR]

Do you have suggestion on how to model the SR latch in this boost converter? It looks like the SR latch can take the invalid state (S=1 R=1) since it has no mechanism to stop this. Is this a certain type of latch or something or is just this a standard SR NAND latch?

 

[ronv]

I think it is set dominate like this. Using it this way the timer can still pulse the FET on.

 

[FusionITR]

I think it is set dominate like this. Using it this way the timer can still pulse the FET on.

If set is dominate, that means the over current protection won't work. Plus in invalid state doesn't it depend on transistor properties (delay time/etc) which Q state it ends up at?

 

[ronv]

if set is dominate, that means the over current protection won't work.

i haven't studied what fires the timer, but yes when the timer is active the current limit will be off (i think)

plus in invalid state doesn't it depend on transistor properties (delay time/etc) which q state it ends up at?

if the set and reset were the same pulse that would be true, but they aren't.

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