Advice on AVRs and PICs please

[ljcox]

I want to design a device that will record the output of an 8 bit A/D converter operating at 20 MHz (ie. 20 M Samples/sec).

Thus I need a PIC, AVR or microprocessor that can read and store in RAM at that rate. The RAM should be able to hold at least 256 bytes.

Can someone suggest a suitable IC please?

Alternatively, I could use a FIFO to store the data and use the PIC or AVR to control and process the data after it is stored (at a lower speed).

Len

 

[Nigel Goodwin]

Presumably this is for an oscilloscope?.

A micro-controller solution isn't going to get any where near those speeds, you need a hardware solution. There are lots of suitable projects on the web, try looking at those.

 

[StupidDum]

20M sampling rate? thats quick. what application is this for? DSP?
PIC can not do that, as its maximum crystal frequency is only 40M

 

[laroche73]

capture device using micros

What kind of trace depth did you have in mind (at a sustained capture rate)? ||Edit||, never mind, just read your post again, 256 bytes.

The following design gives an idea of the limitations of using a micro for real-time sampling. Using the fastest PIC clock rate available (40Mhz), it achieves a sampling rate of 1Mhz. The PIC uses 4 clocks per instruction cycle, so using no more than 10 instructions per input sample gives (25nS x 4 clks) x 10 inst => 1000 nS/sample.

**broken link removed**

Most instructions on the AVR execute in one clock cycle, but the maximum clock speed for most AVRs is limited to 8 or 16Mhz (the latest addition to the MegaAVR family, the ATmega88, can run at 20MHz).

http://www.atmel.com/dyn/products/product_card.asp?PN=ATmega168

The MegaAVR has enough onboard SRAM (1KB - 4KB) to be useful for this kind of application (the mid-range family has up to 512 bytes, @8/16Mhz). Assuming a similar approach to the one outlined in the PIC design note, you might be able to squeak out a 2Mhz sampling rate: 50nS x 10 inst = 500 nS.

Alternatively, I could use a FIFO to store the data and use the PIC or AVR to control and process the data after it is stored (at a lower speed).

Using the micro as a controller is a more practical idea, and will get you to 20Mhz. Of course, your trace depth depends on the FIFO depth. Deep FIFOs are expensive, a lot of designs on the web use counters and fast 32Kx8 or 256Kx16 SRAMs as a low cost alternative. Another option for very deep buffers is DRAM or SDRAM, but there are more issues to consider with these, like handling refresh and row boundries. Hope this helps. - Claude

 

[bmcculla]

This sounds like a good job for an FPGA. 20MHz should be no problem for a Spartan 2E or equivalent. A medium sized CPLD might work too (with an external FIFO or RAM). The micro just has to read out the values that the FPGA stores. Most FPGAs have built in dual port ram which would make a good FIFO.


Brent

 

[ljcox]

Thank you all for those responses.

Yes, Nigel, it is simple a storage oscillscope. I have designed a hardware proposal, but wish to consider a processor controlled one also.

Len

 

[csaba911]

Hello

Here is my idea.

On the simulator the ADC stop round 5Mhz clock speed.
In theory if your ADC is fast enough and you use faster counter "74HCx" it should be able to clock it up to 40 MHz, witch will give you 20Ms for 4096 sample!

If I'm wrong, comment welcome !

Steve

 

[ljcox]

Thanks Steve, I'll look at this idea.

Len