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ADC Signal To Noise Ratio (SNR) Confusion

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shafri

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while searching for 1MSps ADC Chip datasheet. i look at SNR spec and most of them (at least 2 datasheet) showing similar figure. Below is the figure i got from 1MSps MAX153EWP (datasheet here). from what i know, that figure means its only usefull at 195.8KHz (KSps?) then what about and why it is speced at 1MSps? if the SNR at freq other than 195.8K are useless. or maybe i understand it wrongly, does it means the adc is feed with 195.8KHz signal, and the adc conversion is speced at around -80dB noise floor? what i expect is the SNR graph if the chip is to be feed by a range of input frequencies, say 0-1MHz sine input signal, and the graph will show the noise floor for each input frequency? is it too costly for that?

since i'm at this, actually i'm looking for 10bit 1MSps ADC 1Channel input with parallel interface output, SOIC or smaller pitch. still dont have luck finding the right one. if you know some chip to recommend, or have worked with it before, i will appreciate your suggestion. thanks.

fyi: why 10bits? because i want to use 8bit only and since i expect there will be noise creeping in the low 2 bit, so i think i will skip the 2 LSB bit and get cleaner 8 bit in MSB, am i delusional here?
 

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hi,
Its sampling is at 1MHz and the test input frequency is 195KHz, showing a 49dB SNR for that particular test frequency.

Look at this clip from your image.

EDIT:
You do realise you cannot ADC a 1MHz signal with a 1MHz sampling rate.
The ~200Khztest signal has only 5 samples per sine cycle.
 

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Last edited:
yes i know, we cannot sample 1MHz signal at 1MSps... we can actually, but it will give garbage data. let say i want to crank a bit, say 300-500KHz signal. can i expect the SNR the same to this 195.8KHz signal?
 
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