Hello, I have a GPS module, an FPGA spartan 3 development kit and a voltage switch 3.3v -10v and vice versa.
I need to take the 1 pulse per second (PPS) which is coming from the GPS and change its width 80µs to 20µs, rise time to 20ns max and amplitude from 3.3v to 10v.
Everyone is connected to each other with wire wrap.
The width convertion isn't a big deal but the others are really hard to solve. See, the rise time of the PPS with a resonance circuit is less than 20ns, of course the wire wrap isn't ideal for this speed (=coil+capacitor) and I get 50ns rise time thus voltage switching cannot be simultaneousley as the voltage switch has its own rise time, 12ns , which is being added and I get 62ns rise time.
The FPGA is'nt helping either, its signal rise time reachs to 40ns and its best shot is 50ns after the original PPS which is also not good, the delay should be short as possible (0ns-5ns).
The solution for all of this is to use a low jitter clock such as Rubidium clock ,make a frequency divider/multiplier and some Hocus Pocus.-But the problem is that I don't have such clock and I can only use the FPGA clock while is being fixed by its DCM core. In short I need your help.
P.S
All of my measurements were taken by digital scope.
I need to take the 1 pulse per second (PPS) which is coming from the GPS and change its width 80µs to 20µs, rise time to 20ns max and amplitude from 3.3v to 10v.
Everyone is connected to each other with wire wrap.
The width convertion isn't a big deal but the others are really hard to solve. See, the rise time of the PPS with a resonance circuit is less than 20ns, of course the wire wrap isn't ideal for this speed (=coil+capacitor) and I get 50ns rise time thus voltage switching cannot be simultaneousley as the voltage switch has its own rise time, 12ns , which is being added and I get 62ns rise time.
The FPGA is'nt helping either, its signal rise time reachs to 40ns and its best shot is 50ns after the original PPS which is also not good, the delay should be short as possible (0ns-5ns).
The solution for all of this is to use a low jitter clock such as Rubidium clock ,make a frequency divider/multiplier and some Hocus Pocus.-But the problem is that I don't have such clock and I can only use the FPGA clock while is being fixed by its DCM core. In short I need your help.
P.S
All of my measurements were taken by digital scope.
