a small MOS characteristic question

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qtommer

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ive attached a simulation result of the characteristics of a NMOS transistor to observe the effect of the presence and absence of a gate voltage on the output of the NMOS.

In the absence of the gate voltage, when Vg=0, it is observed that the output voltage will be equivalent to the last previous voltage state when Vg was applied.

What is the reason for this occurence where the output will remain in the state of the previous last voltage input state when the gate voltage transits from HIGH to LOW?

thanks!
 

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hi,
When you say In the absence of the gate voltage, when Vg=0, do you mean when the Gate is disconnected and 'floating'
 
I think you must mean floating (no input). If it were to go to 0 volts assuming the source is at 0 volts it would turn off. The reason - nothing to remove the gate charge.
 
Last edited:

It sounds like a Simulation artefact, this should not happen in a real MOSFET
 
It looks like you are not fully turning on the MOSFET. What is the required MOSFET turn-on gate voltage?

Show us the test circuit and the MOSFET part number.
 
The gate is also a capacitor, so it stores the last input unless it is drained by a resistor from gate to source. Other wise it is floating and stays at it's last input.
 
thank you all so much..i understand now...=) im actually not simulating a circuit but a vlsi layout in microwind.

btw. I was just wondering, an NMOS drives a good Logic 0 but a bad Logic 1 because of the voltage drop required to overcome VTH (Threshold Voltage)
the PMOS on the other hand drives a good Logic 1 but a bad Logic 0 ( Because it;s 0V + VTH) what is the mechanism of the MOS operation that causes this adding of VTH?

Thank you all so much=)
 
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