74hc595 shift register question.

[dr pepper]

Quick question on this chip.

If I tie the latch enable pin permanently high, will the data being shifted into the serial register appear immediately on the outputs, ie does the latch go transparent.
Flicking through the datsheet it says that if you connect the serial register and the latch register clock inputs togther the o/p will allways be 1 clock pulse behind, making me think theres some weird syncro stuff going on.
I'd like to use one of these instead of a 74hc164 as I have a drawer full.

 

[ericgibbs]

hi,
This is a clip from the d/sheet, its a Low to High transition of the Latch Clock.
Is this the pin you are querying.?

I don't see a Latch enable, only an output enable.

 

[dr pepper]

There are diffrent legends for the same pins on various sheets!

In essence what I'm saying is that if I tie the latch enable/latch clock/data transfer or whatever its called to active (high) would the latch become transparent, meaning would the o/p from the latch match the i/p, in other words the 'hc595 would behave like a 'hc164.

The datasheet eric just posted shows latch clock edges further making m think its not going to work.

 

[ericgibbs]

I would suggest a quick hardware test with an actual HC595, a bread board circuit should show how the pin works.
Let us know what you find.
E

 

[dr pepper]

Yup will do as soon as I get home.

 

[crutschow]

.................
If I tie the latch enable pin permanently high, will the data being shifted into the serial register appear immediately on the outputs, ie does the latch go transparent.
Flicking through the datsheet it says that if you connect the serial register and the latch register clock inputs togther the o/p will allways be 1 clock pulse behind, making me think theres some weird syncro stuff going on.
............

I don't think it's "weird syncro stuff", it's just the way a clocked latch works.
It's similar to having two flip-flops in series with a common clock.
The second FF's output will always be one clock delay from the first FF's output (like a shift register operates).
So I suspect that's how the 74hc595 output latch operates.

If you want to minimize the delay between the S/R bit change and the latch output, then you can delay the S/R clock to clock the latch after the S/R output settles where the delay is slightly longer than the clock setup time [SRCLR high (inactive) before SRCLK ↑ in the data sheet].
A Schmitt trigger (such as two 74HC14 Schmitt inverters in series), with possibly a small RC delay at its input if needed, can provide this clock delay.

 

[dr pepper]

I did something like that but simpler, the chip tolerates slow transition times so I put a r/c on the shift reg clock pin, delayed that slightly to the latch pin, now the shift reg clock also latches the latch a few us after the clock pulse.

 

[crutschow]

I did something like that but simpler, the chip tolerates slow transition times so I put a r/c on the shift reg clock pin, delayed that slightly to the latch pin, now the shift reg clock also latches the latch a few us after the clock pulse.

Great. Whatever works.
But I don't see why you delayed the clock pin (if I understand correctly). Only the latch pin needs the delay.

 

[dr pepper]

Terminology again, and probably my fault, let me say that again,
I have 2 lines into the chip, data and clock, data goes to data in on the register, clock goes to the register clock input and then delayed through an r/c into the latch enable input, so the regsister shifts data in, then a few us after the latch is latched, effectively removing the latch section of the chip, its acting like an unlatched shift register, pointless but saves me having to buy parts.

Kinda gives me another idea, I could probably have 2 r/c delays and have a shift register driven by 1 pin, in fact I could have half a dozen daisy chained, cool for driving leds.

 

[crutschow]

I did something like that but simpler, the chip tolerates slow transition times ...................

I don't understand that.
The data sheet (page 5) has stated limitations on the input rise and fall times.

 

[dr pepper]

Hmm I would agree looking at that sheet.
The devices I'm using are NXP, looks like again there are diffrent properties from diffrent manufacts.

 

[crutschow]

Hmm I would agree looking at that sheet.
The devices I'm using are NXP, looks like again there are diffrent properties from diffrent manufacts.

Look at Table 9 of this.
Similar info, just presented differently.

 

[atferrari]

Are you trying to save a pin?

I recall using 4 of these chips, cascaded and just 2 pins: one for the shifting and one for the latching.

Easy to test in breadboard BTW.

 

[dr pepper]

OK then, only I'm using 10n.
Yes and no, not so much saving a pin, I wanted to use a '595 as an unlatched register.
I succeeded.

 

[ericgibbs]

Pleased to hear that you have a solution.
Post a description of the method used.
E

 

[dr pepper]

I dont have a schem package that will upload, however roman has done something very similar only with lcd's:

https://www.romanblack.com/shift1.htm

Only I used a 10n and 3k3 to delay the shift clock to the latch enable, and my system is 2 wire.
Looks like roman's allready thought of the 1 wire system, and made an application for it, I might do that on another project.