74hc594 sipo SHIFT REGISTER

[uceesdp]

Hi all,

If send in 4 bits of data serially (Q1-Q4), when should I pulse the SRCLK pin to store this data. In the information section of this website, the SRCLK pulse started between t4 and t5.

Can I pulse the SRCLK on t4 or t5 to retrieve the 4 bits of data?

Thanks

 

[Dr_Doggy]

you put a 1/4 signal of shift clock to store clock,


store = shift/4

putting a latch on the output wont help since your signal wont go to output until you hit the store latch

 

[uceesdp]

hi,

Is that between t4 and t5 because that makes life difficult rather than just clocking the signal as soon as the RCLK goes high.

The RCLK controls a 4 bit binary counter. When the counter reaches 4, it produces a postive-edge pulse on the SRCLK pin via a 555 monostable. This does not work. Any solutions on how to store on a shift/4 without another clock because its extremely hard to synchronise both clocks?

thanks

 

[Blueteeth]

I'm unsure of exactly what you wish to do, but I think you want to 'automatically' load in your 4 bits from the internal shift registers to the latch output... correct? I can only assume you want to use 2 lines, serial data, and serial clock - with the 'latch' being derived from the serial clock.

Now, its easy to get confused as different schematics/datasheets have different names for 'serial clock' and 'load clock'. The '594 and '595 generally use SRCLK and RCLK. You must be consistant with names, here I am going to use 'shift clock' and 'load' to indicate to clock to shift bits into the shift register, and 'load' for the latch out the output.

In order to 'latch' (using 'load', or RCLK as it is in the datasheet) after 4 bits have been shifted in, you should make this line high after the 4th serial clock, but before the 5th. I suspect your 4 bit counter is outputting a high as soon as the count reaches 4, effectively, loading the latch instantly *as* your 4th bit is loaded. A monostable is a good way of delaying, but relies on analogue timing components.

You may be able to do this with a single transistor with your counter. Use a PNP with its emitter (positive) connected to the output of your 4-bit counter. And its base connected to your shift clock via a resistor. It's collector is connected to your 'load' line. It'll make a crude logic gate, meaning its output will only be 'high', when your count is '4', and your clock is '0'. It'll delay the 'load' line by 1/2 of your shift clock. Although, with this method you may have to reset the counter afterwards... since the counter will start at '0', after 4 clocks, it'll be '4', after another 4...it'll be 8. The above method only works if you're counter has a single 'pulse' output :/

What binary counter did you use?

 

[Dr_Doggy]

Rclk is the edged switch to store the data in to the register, you wont have any data on your output until rclk is pulsed, also note that it is positive edged so that means it only opens the gate for the moment that rclk signal goes from 0v-5v, so if rclk has either a constant 0v or constant 5v nothing will input

if you really want to reset on Q5(output 5 high) then hook sclk and rclk together, then invert Q5 and run it in to RCLR,
but with this config the register will show the data shifting in each step, which may give you confusing data at your output, depending on what your feeding, also if your first bit(s) of data is 0 , it may reset a few steps late