74HC373 + 8051

I have a question.

I have seen many schematics where a 74HC373 can act as a buffer between the ROM and the 8051.

Every time I connect it, and convert it to PCB, wires seem to be criss-crossed when I think they shouldn't be.

How do I optimize the 74HC373 so that I can treat it as if the data pinout was similar to a 74HC245 pinout.

Take a crayon an write "74hc245" on it.

Why not just use a '245 - they cost less than a candybar (or a crayon).

On the '373, When the latch enable is high, the outputs follow the inputs.

hyedenny said:

Take a crayon an write "74hc245" on it.

Why not just use a '245 - they cost less than a candybar (or a crayon).

On the '373, When the latch enable is high, the outputs follow the inputs.

Click to expand...

LOL :lol: no.

When I tried it with the 74HC245, it didnt work. Everyone gave me the insight (or should I say realization?) that the 74HC245 functions as a basic buffer, and the 74HC373 is actually an 8-bit flip-flop which is level-triggered. and storage is enabled when the clock pin is high. when it is low, new data cannot change the existing data.

The 74HC573 works better, but it costs about 50% more money! ($1 as opposed to 70 cents).

ONE DOLLAR!!!!! Holy cow!

Theyre only .31 at Jameco!

At Mike Quinns's (RIP) they were about a dollar for a whole handfull of 'em.... And I have big hands!

I guess that's what happens when I see what I buy!

I buy my parts in the store. I don't order online.

The 373 is not supposed to be a buffer. It is supposed to latch the low order address lines which are multiplexed with the data lines.

A 245 is a bidirectional buffer used for a bidirectional data bus.

You might actually end up using both in a single design but you have to think about which one goes where and how to generate the control signals.

Papabravo said:

The 373 is not supposed to be a buffer. It is supposed to latch the low order address lines which are multiplexed with the data lines.

A 245 is a bidirectional buffer used for a bidirectional data bus.

You might actually end up using both in a single design but you have to think about which one goes where and how to generate the control signals.

Click to expand...

After I played with the 74HC373 by itself, here is the truth table that is correct:


74HC373:
Clock Input: High
Data Input: Any
Output: Same as Data Input

Clock Input: Low
Data Input Any
Output: Data input ignored

74HC245:
Enable Input: High
Data Input: Any
Output: Low

Enable Input: Low
Data Input: Any
Output: Same as Data Input


The "Enable Input" refers to the direction pin and the chip enable pin, and it is assumed that data is transferred from "B" to "A".

The logic table assumes that the 74HC373 latch is enabled in the circuit.

So I'm finding that the only difference between a 74xx273 and the 74xx374 in terms of basic operation is that the 74xx273 has a clock that is edge-triggered, while the 74xx374 is level-triggered.

When I tried my first microcontroller, I didn't realize that the first 8 address bits must be stored in an external buffer when trying to access the data.

mstechca said:

When I tried my first microcontroller, I didn't realize that the first 8 address bits must be stored in an external buffer when trying to access the data.

Click to expand...

Except it's not really a micro-controller, a micro-controller is a single chip that needs no other support chips - why on earth you're wanting to go back 30 years and use old micro-processors instead of modern micro-controllers still makes no sense?.

I prefer to use 74HC573 than 74HC373. The prior one has pinout similar to 74HC245. No criss-crossing tracks on PCB.

A 74XX273 and 74XX374 are BOTH positive edge triggered Flip-Flops. The difference is that the 74XX374 outputs can be tri-stated or made high impeadance. The 74XX273 outputs are always driving either high or low. They cannot be made high impeadance.

NOTE: A latch, a buffer, and a flip-flop are all different animals. Please don't think that they are interchangeable in ANY meaningful way. That pathway will lead to despair and desparation.

$1 for a 74xx245, wow What store, Radio Shack? That is all we have left where I live and that selection is gone.

Also, I am with Nigel, the uC is all self contained. And if you are like me (lazy), I use the internal osc. most of the time and save 3 more parts. That is if I am not going fast, doing misson critical timing, or using it for serial communications..

mstechca. I will dig up all the DS5000 (I think it was), 8031 and 8051 chips I have an make you a great deal. And tubes of EPROMs as well, will throw in a UV eraser too (I use it to clean AC vents and bathroom shower now). Think I have tubes of 245, 244, 373, etc..

But I have a lot of them and have not opened that box in a long time.
Get into the PIC and Atmel chips. Programmers are easy to build, software pretty much free.

Heres my thoughts, and hopefully I am right because I am about to try to fab a pcb to implement this...

The 74hc373 is an 8bit tri-state (hi impedance) latch.

Interfacing to a uC/uP is generally done by connecting the G/LE to the processors ALE/P line. This line is toggled when doing external memory addressing and causes your ADDRESS (which is now on the connected DATA pins) to be stored in the LATCH (373).

Next the ALE/P line goes back to normal and the actual data you wish to send is outputted on your DATA lines. But since, the 373 is latched, it still holds your address for use by your external memory or FPGA etc.

So you have 8bit ADDRESS in the latch, and 8bit DATA on the outputs (same ones that loaded the 373 in the first place)

It's really best to let sleeping threads lie. Check the date on the post before yours.

I was hoping someone would correct me if I was wrong since I am about to implement the theory.

The key feature of the 373 is that it is transparent, while latch enable (LE) is high. That means the outputs are equal to the inputs with a small propagation delay. Connect ALE directly to latch enable. The Address on AD[7..0] flow through while ALE is high and is latched on the trailing edge. After the trailine edge of ALE either the processor or another peripheral can drive AD[7..0] and the latch outputs are unaffected. Any decoder on A[7..0], on the output of the latch, will have plenty of time to settle before the falling edge of RD* or WR*.

An octal FLIP_FLOP will not perform nearly as well for reasons that should be altogether manifest.

Don't forget the high order address lines on P2. It is up to you if you want to use them or not. They are valid from shortly after ALE rising until either RD* or WR* or PSEN* rising.

Q: How do you know if you are using A[15..8] or not?
A: It depends on the instruction you use in the firmware. If you use a MOVX with the @DPTR then you're using the high order address bits. If you use the MOVX with @R0 or @R1 then you are using an 8-bit address for the external reference.

Excellent, I think Im good to go then! Thanks PapaB.