I am using the attached circuit to double my VARIABLE frequency,which produces a nonsymmetric pulse based on a not gate's delay.
Because I am feeding some and gates through latches and these are me latches enables,I need it to be perfect 50%,without change in frequency.
I am doing this in Xilinix Foundation's software's schematic editor which provides me with just simple logic gates.(no cap or IC)
Actually I am trying to make LS7084 IC through FPGAs.
But finally I reached my goal through another way with no 50% duty cycle pulse.
(but I still don't know how can I make my pulse symmetric with flip-flop without changing it's frequency :roll: )
Thank you all for your attention