30 ns TLL signal delay - How to?

[winterhunter]

Dear all,

I was looking into connecting an external SRAM to a PIC18.

In order to avoid dedicating 24 pins (8 data + 14 address + 1 write enable + read enable), I'd rather use 3 bus transceivers (74LS245). Also, I would like to use the same pin to control direction (on the 74LS245) and read enable (on the SRAM - I could later extend the same principle to write enable). One could say that I'm building an ancient ancestor of a computer northbridge...

However, to get a correct timing while taking advantage of the fact that the SRAM is faster than the µcontroller, I would need to be able to send the RE signal around 20 ns latter than the direction signal (for reading it could work without the delay, but for writing a precise sequence is needed to ensure data integrity).

To be on the safe side of things, I would need a 30 ns delay on the signal... How do I implement it?

Thanks

Gonzalo

 

[Leftyretro]

Dear all,

I was looking into connecting an external SRAM to a PIC18.

In order to avoid dedicating 24 pins (8 data + 14 address + 1 write enable + read enable), I'd rather use 3 bus transceivers (74LS245). Also, I would like to use the same pin to control direction (on the 74LS245) and read enable (on the SRAM - I could later extend the same principle to write enable). One could say that I'm building an ancient ancestor of a computer northbridge...

However, to get a correct timing while taking advantage of the fact that the SRAM is faster than the µcontroller, I would need to be able to send the RE signal around 20 ns latter than the direction signal (for reading it could work without the delay, but for writing a precise sequence is needed to ensure data integrity).

To be on the safe side of things, I would need a 30 ns delay on the signal... How do I implement it?

Thanks

Gonzalo

Well you could pass the signal through a series of inverter gates such that the total time to pass is 30ns, see spec sheet on device you select (propagation delay spec). Or you could find one of the old logic level delay modules, they were available in DIP packages, were logic level compatible and many even had taps to select increments of delay time.

Lefty

 

[kjennejohn]

try latches instead...

Hi.
Consider using octal latches (74xxx373 for instance) instead of the -245 buffer. One port of 8 pins can feed two 8-bit latches with the address (16 bits, 64Kbytes!), then read or write data with the same port. This one port does triple duty: 1. put out address bytes, low and high, 2. write out data, 3. or read in data. That saves you 16 pins for dedicated addressing right off. However, you have to use two pins to drive a strobe pin at each latch (2 latches, 1 pin each). And you still need the three control pins: -OE, -CS, and -WR (depends on SRAM model).

We are talking a total of 8+2+3 = 13 pins, where you need 24 pins when using buffers. You save 11 pins.
But, the trade off is time. You now do your memory access in multiple steps, each step taking several instructions. Response time of the SRAM is no longer a problem when using latches, however. Remember, a port is basically a latch. I doubt you can outrun an SRAM's response with a processor, unless the SRAM is reallly slow and the processor reallly fast.

END TWO CENTS
kenjj

 

[winterhunter]

Thanks for your input!

One question though:
I have seen two types of latches available at my usual shop, 74LS259 and the one you mentioned (74LS373). To my (very newbie) eyes, I would say that the former is better suited. Am I wrong?

 

[ericgibbs]

hi winterhunter,

The 74259 is an addressable latch, you would have to sequentially address each individual latch bit, in order to load an 8 bit byte [ refer pins 1,2,3] on the device.

The 74373 latches all 8 bits in one operation.

Eric

 

[Dean Huster]

But regarding development of delay, rather than using a lot of standard logic inverters to create the delay, use far fewer chips of a slower logic family such as 4000-series CMOS or 74Lxx (if you can find any).

Dean

 

[winterhunter]

@Ericgibbs:
Thanks a lot!

 

[ericgibbs]

hi gonzalo,

You may find the Z84C90 from Zilog interesting.

Ive been considering interfacing it to a PIC, mainly for the RS232 features.
Have used it many times with earlier CPU's.

Eric