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3 inputs to 2 outputs

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svtiss

New Member
Hi
I need to decode 3 lines to 2
here it is
000 to 00
001 to 01
011 to 10
111 to 11

Anybody knows an IC decoder or whatever can do this , and I have 15v signals
Pls help , thanks
 
This is a simple gating problem so you don't need a special IC (I doubt that you'll find one anyway). Draw Karnaugh maps and devise the simplest realisation.

Don't know what a Karnaugh map is? Try searching for it in this forum or Google.
 
And what do you want to do with the "don't care" states?

If they can be either 0 or 1, then all you need is a Quad NAND gate.
 
I have only 4 situations and there no dont care states , I think how easy to do it, use gates or one IC decoder or something
 
svtiss said:
I have only 4 situations and there no dont care states , I think how easy to do it, use gates or one IC decoder or something
So if there are no "don't care" states, what outputs do you want in the unlisted states?

This what you posted:-

000 to 00
001 to 01
011 to 10
111 to 11

So what outputs do you want from:-

010
100
101
110

?
 
thank all
ok again about
I have only 4 states on inputs here is the table

input outputs
-------l---------
000 l 00
001 l 01
011 l 10
111 l 11

that all what i need , so i wont have others states
 
svtiss said:
thank all
ok again about
I have only 4 states on inputs here is the table

input outputs
-------l---------
000 l 00
001 l 01
011 l 10
111 l 11

that all what i need , so i wont have others states
Therefore, all you need then is a Quad NAND gate.
CBA YX
000 l 00
001 l 01
011 l 10
111 l 11

So it can be realised by the following Boolean functions

Y = B and X = C + AB'.

These are easily realised with a Quad NAND gate.
 
Last edited:
svtiss said:
Hi
I need to decode 3 lines to 2
here it is
000 to 00
001 to 01
011 to 10
111 to 11

Anybody knows an IC decoder or whatever can do this , and I have 15v signals
Pls help , thanks

This decoder could be implemented in a single PAL IC, like PALC16V8 using VHDL language and her is the code for it

library ieee ;
use ieee.std_logic_1164.all;
entity decoder is
port (
a, b, c : in std_logic ;
y : out std_logic_vector (1 downto 0) ) ;
end decoder ;

architecture behavior of decoder is
signal abc : std_logic_vector (2 downto 0) ;
begin
abc <= a & b & c ;
with abc select y <=
"00" when "000",
"01" when "001",
"10" when "011",
"11" when "111",
end behavior ;
 
This is a complicated way of doing something simple.

As I wrote above, all that is required is a cheap NAND gate package.
 
Thanks for help
I tried many ways how to do the project and found that 3 relays can do everything what I need .
 
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