Welcome to our site!

Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

  • Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

2D-Mesh Chip-to-Chip network Routing Algorithm

Status
Not open for further replies.

tonionio

New Member
Hello everyone and nice to be here with you guys in such an interesting forum!

I would like to ask for advice. My project is to write a routing algorithm for a 64core chip using dimension order routing. In the beginning I should write something simple and then maybe implement other features in the algorithm in order to improve traffic distribution.

Each core's router will have 5 ports , 4 ports for east , south ,west, north and a local port for the processing unit.

I want to use as the title says x-y routing and write the code in VHDL as it is a safe way to get results. As i ve seen the most common tool is Verilog but I have some hands-on experience in VHDL so my supervisor said to go on that way.

The algorithm is going to be implemented on a board with 4 FPGA's each one implementing 16 cores (4x4) of the total 64 cores.

The project is all about delay of such a routing algorithm and comparison with delay of optical interconnects instead of wires.

Any suggestions to where I could find code or tutorials to begin the build for a router?

Any help and any suggestion is most welcomed.

Thank you in advance.
 
Status
Not open for further replies.

Latest threads

Top