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18F1320 A/D Conversion

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UTMonkey

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Hi All,

Just reading up on the A\D Module of this chip and want to have a go at sampling voltages.

The datasheet for the chip suggests:-
The Maximum recommended impedence for analog sources is 2.5k

For my first prog I just want to have a pot which I can adjust to get a reading from the module, if I undertand "impedence" correctly does that mean that the choice of pot should'nt exceed 2.5k?

Thanks in advance?

Mark
 
Not exactly - but you shouldn't use too higher a value - a 10K or 4.7K pot will be OK anyway - using a 100K or 220K pot though will mean it takes a MUCH greater time for the sample and hold to settle when you change channels.
 
Thanks Nigel, I might enquire later about getting more information about "Impedence", it is rather suprising how much electronics books DON'T discuss it (at least at length).

Perhaps it is because it is a straightforward concept?

Mark
 
UTMonkey said:
For my first prog I just want to have a pot which I can adjust to get a reading from the module, if I undertand "impedence" correctly does that mean that the choice of pot should'nt exceed 2.5k?
Actually, the maximum pot resistance can be 10K before degradation of the ADC samplings occur. At mid-position the wiper of the pot will have a thevenin resistance of 2.5K because the two legs will both equal 5K and will be in parallel as far as AC currents are concerned. Google for "Thevenin's theorem" if you want to know more.
 
If your just reading the pots the 10K ones on Junebug work well. Only if you start sampling at very high rates will you see any problems with 10K. You have to give that little A/D sampling cap some time to discharge.
 
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