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12F683 PIR1 vs PIE1 confusion for Timer1 and Timer2

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jess

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I've been looking at the initialization routines for Timer1 and Timer2 in the PICmicro Mid-Range MCU Family Reference Manual - the manual can be found at

https://www.electro-tech-online.com/custompdfs/2006/12/33023a.pdf.

I think its an excellent reference for the newby I am.

The PIR1 and PIE1 registers control operation of interrupts for the timers. They are located at 0Ch and 8Ch respectively according to Figure 2 of the 12F683 data sheet and in detail in Registers 2-4 and 2-5. They are extremely similar, one being flag bits and the other enable bits.

However, when I go into Project and do a Quickbuild, and VIEW the Program Memory I see the same machine code is produced for both PIR1 and PIE1 registers. It is 018C hex for both, and both show PIR1 in the machine code.

Assuming 01 is the CLRF op code and 8C is the address (for CLRF PIE1), I tried entering 010C (CLRF PIR1) in the program memory display and clicked on it. It compiles to a CLRW mnemonic not CLRF PIR1.

So, WHAT am I missing here? I assume the routines work but I don't understand this. Anyone have an explanation? I'm using MPLAB v7.40.

Thanks

jess
 
jess said:
I've been looking at the initialization routines for Timer1 and Timer2 in the PICmicro Mid-Range MCU Family Reference Manual - the manual can be found at

https://www.electro-tech-online.com/custompdfs/2006/12/33023a-1.pdf.

I think its an excellent reference for the newby I am.

The PIR1 and PIE1 registers control operation of interrupts for the timers. They are located at 0Ch and 8Ch respectively according to Figure 2 of the 12F683 data sheet and in detail in Registers 2-4 and 2-5. They are extremely similar, one being flag bits and the other enable bits.

However, when I go into Project and do a Quickbuild, and VIEW the Program Memory I see the same machine code is produced for both PIR1 and PIE1 registers. It is 018C hex for both, and both show PIR1 in the machine code.

Assuming 01 is the CLRF op code and 8C is the address (for CLRF PIE1), I tried entering 010C (CLRF PIR1) in the program memory display and clicked on it. It compiles to a CLRW mnemonic not CLRF PIR1.

So, WHAT am I missing here? I assume the routines work but I don't understand this. Anyone have an explanation? I'm using MPLAB v7.40.

Thanks

jess
The instructions are context sensitive. What does that mean? Locations in the register file are accessed in multiple banks because there are not enough register file address bits in the instruction. The other register file address bit(s) are in the STATUS register. The bit is called RP0 and it is bit 5 of the STATUS register. Refer to figure 2-2 on page 8 of the 12F683 datasheet for a picture of the two register banks. You should be able to locate the bank switching code as follows:
Code:
    bsf   STATUS,5  ; select Bank 1
    ....
    ....
    bcf   STATUS,5  ; select Bank 0
So when RP0 = 0 register file locations are in Bank 0, and when RP0 = 1 then register file addresses are in Bank 1.

Got the picture?
 
Thanks for the comments but I'm still a bit confused. I'm aware of Bank 0 and Bank 1 and bank switching. However the machine code produced was the same for both PIR1 and PIE1 (018Ch).

Mike, K8LH, used Timer2 in some timing in an RS-232 program (12F683 Serial.asm). In it the CLRF PIE1 was listed in the machine code as PIR1 018Ch (note the name change from PIE1 to PIR1). A few lines below, a CLRF PIR1 was compiled to PIR1 018CH.

Also, PIR1, a Bank 0 register (in Bank 0 so no bank switching is involved) is compiled to 018Ch, an apparent Bank 1 address. Why isn't that 010Ch (except that is the CLRW command)?

So... as long as the processor knows what's happening it doesn't matter if I'm confused momentarily and recognize that the machine code may not look like I'd expect it to. I just need to be aware of which bank its in and to interpret accordingly and possibly still be confused. That's OK, I'm usually confused about something.

Now, does that mean that I can use the names PIE1 and PIR1 interchangably as long as I get them in the proper Bank? Think I'll try changing them to see what happens. Hopefully getting the names wrong will flag an error message.

Does this happen with other "adjacent" (or 80h offset) Bank 0 and Bank 1 registers? I'll try and check on that.

Many thanks for the comments.

Jess
 
Hi Jess,

Accessing the GPR and SFR registers on the 14-bit core PIC processors can be frustrating at first but it sounds like you're getting a handle on it.

Instructions that access file registers at 020h, 0A0h, 120h, and 1A0h will all look the same. The microcontroller relies on the RP0 and RP1 bits in the STATUS register to resolve the b6 and b7 portion of the file register address.

Happy Holidays. Mike

Code:
;
        clrf    STATUS          ; force bank 0              |B0
        clrf    PORTB           ; clr PORTB output latches  |B0
        bsf     STATUS,RP0      ; bank 1                    |B1
        clrf    TRISB           ; set PORTB all outputs     |B1
        bcf     STATUS,RP0      ; bank 0                    |B0
;
;  as you've already guessed, the code below will 
;  access the TRISB register in bank 1
;
        clrf    STATUS          ; force bank 0              |B0
        clrf    PORTB           ; clr PORTB output latches  |B0
        bsf     STATUS,RP0      ; bank 1                    |B1
        clrf    PORTB           ; set PORTB all outputs     |B1 <- TRISB
        bcf     STATUS,RP0      ; bank 0                    |B0
;
 
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