Schmitt logic gates such as in the CD4093 quad NAND gate IC are useful buiding blocks for various functions. The example functions shown here are oscillator, bistable, RS latch and monostable. I don't claim any originality for these, but thought it useful to bring them together for the benefit of newbies.
The oscillator in circuit A is simple in the extreme but works reliably (albeit subject to slight frequency drift with temperature and supply voltage) over a huge range of frequencies, with a period from microseconds to minutes. An advantage is that a polarised electrolytic capacitor can be used (if necessary) for the timing cap C1. The period T is ~ 0.68*R1*C1. One input of the gate can be used to enable/disable the oscillator.
Bistable circuit B is flipped from one state to the other by brief closure of the switch. The time constant R3*C2 should be greater than the time for which the switch is closed.
The RS latch in circuit C is set (Q goes high) by taking the Set input low, and is reset by taking the Reset input low.
The monostables in circuits D and E are triggered by negative-going pulses. Circuit D is configured to allow the use of a polarised electolytic timing capacitor if necessary (for long timing periods) whereas circuit E is not (so is more suited to short timing periods). Because of the different configuration the timing periods for D and E differ slightly. In circuit E resistor R6 limits current through the inbuilt protective diodes in the gate U9, but is not strictly necessary for a low value ( < ~10n) C4.
The oscillator in circuit A is simple in the extreme but works reliably (albeit subject to slight frequency drift with temperature and supply voltage) over a huge range of frequencies, with a period from microseconds to minutes. An advantage is that a polarised electrolytic capacitor can be used (if necessary) for the timing cap C1. The period T is ~ 0.68*R1*C1. One input of the gate can be used to enable/disable the oscillator.
Bistable circuit B is flipped from one state to the other by brief closure of the switch. The time constant R3*C2 should be greater than the time for which the switch is closed.
The RS latch in circuit C is set (Q goes high) by taking the Set input low, and is reset by taking the Reset input low.
The monostables in circuits D and E are triggered by negative-going pulses. Circuit D is configured to allow the use of a polarised electolytic timing capacitor if necessary (for long timing periods) whereas circuit E is not (so is more suited to short timing periods). Because of the different configuration the timing periods for D and E differ slightly. In circuit E resistor R6 limits current through the inbuilt protective diodes in the gate U9, but is not strictly necessary for a low value ( < ~10n) C4.