Why has such a big ground plane been used on this switch mode buck led driver?

[Flyback]

The following ZXLD1370 Buck LED driver evaluation board document shows the schematic on page 2 and the PCB layout (top and bottom layers) on page 6.
ZXLD1370 Evalution board (switch mode buck led driver)
**broken link removed**
Note how the ground plane on the bottom layer extends completely underneath the power inductor, L1.
Why did they not make the ground plane less extensive and instead use some of the bottom layer area beneath the power inductor as thermal spreading copper for the inductor? (they could have used thermal vias to conduct heat down to the bottom copper layer from the inductor).
I am speaking about the “LEDK” net, to which one pad of the power inductor is connected…….ie, why isn’t the “LEDK” net used on the bottom layer, as spreading copper for the power inductor?
Aren’t they just blindly putting in a ground plane for no reason? Obviously a certain amount of ground plane is suitable for the control ground, but not the huge ground area seen on the bottom layer of page 6. Why have they used such a big extensive ground plane?

The principles of laying out this kind of switching supply, are
1…Make all switching power current loops as narrow in area_contained as possible
2…..Do not run power switching currents through lengths of control ground.

…none of the above requirements calls for an extensive ground plane in such a buck led driver as this…..so why have they used such an extensive ground plane?…after all, the copper area used for ground could have been used for thermal spreading copper for the power components (FET, diode and inductor).

 

[tronitech]

Perhaps it all boils down to cost? It's cheaper to leave the copper on than etch it away.

 

[Flyback]

thanks, but we don't have to etch it away....just use it for thermal spreading copper.....not ground, which isn't connected to all of the power components.

I am sure you will agree that Switch mode supplies tend to need "star-grounding", and not just mindless use of a large overall, all-covering ground plane?

 

[JimB]

Had you ever considered that it may be like that to minimise radiated emissions from single traces carrying high frequency signals?

You have heared of EMC, havn't you?
All your designs do have filters to prevent conducted emissions along the wiring to both the supply and the load, don't they?

JimB

 

[Flyback]

Had you ever considered that it may be like that to minimise radiated emissions from single traces carrying high frequency signals?

the way to minimise radiation is to make the switching power current loops of the smps as narrow in area as possible........that is not always achieved by just throwing in a ground plane.....in SMPS, the technique of star grounding is more applicable than just pouring in a huge ground plane fill.
Just because a large ground fill is not used all over the pcb, doesn't mean you cannot use filters etc.

 

[ronsimpson]

I would have done it this way. For all the reasons stated above.

 

[Flyback]

why no thermal copper under the inductors "LEDK" pad, connected to the inductor's LEDK pad by thermal vias.?

Please observe the size of the power switch loop...from C3 vin pad....then through R1 and R2, then through C3 and C5, then all the way round to L1's LEDK pad, then through fet drain...source...and back to C3 again..........
..that is a loop with a very unecesarily wide area. Surely you agree?
In fact, its about as wide as it could be on that size of board...very poor layout
And why no thermal copper below L1 LEDK pad?, connected to that pad by thermal vias
Ditto thermal copper for R1 and R2 LEDA pads.

 

[simonbramble]

You are misunderstanding the principle of the ‘loop’. In a dc/dc converter, you have to keep the ‘hot loop’ area small. This is the area that carries the high di/dt.

In a boost converter, this does not include the inductor, since any current flowing through the inductor will have a slow di/dt and the inductor current continues to flow whether the FET is on or off.
During the inductor charge cycle, the current flows through R1/R2, through the inductor, through the FET and down to ground. This is NOT the hot loop.
During discharge, the current continues to flow through R1/R2 and the inductor, but no longer flows through the FET. Instead it flows through the diode, D1.
The hot loop is DIFFERENCE in the above 2 current paths and is the one carrying the high di/dt. Thus the FET and diode, D1, both experience a high change in current with time (di/dt) as the FET switches OFF, so this is the hot loop: through the FET, through D1, into the input decoupling caps and down the ground… back to the FET’s source. This is the path that you must keep small. It does not include the inductor.
In this design, the hot loop is good and cannot really be made any smaller.
You don’t want to put an isolated ground plane under the inductor as the inductor has a high dv/dt at the switch node. Adding copper that oscillates with rise times of 10ns or so will not improve your EMI. As a general rule a solid uninterrupted ground plane will give the best performance EMI wise. If your inductor produces too much heat, pick another inductor.
I have no problems with this board layout. I have a problem with the fact that they are not using an LTC device, but the board layout is good. I’m not sure what is happening with the size of that rectifier diode…..
LTC has an article on hot loops on its website and it is the best one I have seen on this subject. You might also want to see www.sigcon.com

 

[Flyback]

Thankyou very much for spending your time in reply, I appreciate that you are just coming to this in passing, and not having had time to read it fully as have I myself. Your points are of course, very worthy and interesting.

Adding copper that oscillates with rise times of 10ns or so will not improve your EMI

Sorry but this was not what was suggested. You are absolutely right to suggest that it would be a mistake to go putting large thermal copper pours of switching node copper....I would agree with that...but the inductor has one terminal pad connected to the cathode of the "bottom" led in the load.....this does not have high dv/dt and should be used under the inductor to give extra cooling. The inductor carries 9 amps here. Adding copper in such a way under the inductor is free of charge and does not increase the board size, wheras picking a new inductor, a bigger one, may make it higher in profile etc.

I did indeed forget about the hot loop as you describe.....the current that is high di/dt in this loop that you describe, is the reverse recovery current of the power diode...if its a schottky diode , then as you know, its not reverse recovery, but the capacitive current associated with the capacitance of the schottky.
In truth, if the power switch loop and the rectifier loop are kept narrow area, then the hot loop is going to be narrow area too, since its comprised of bits of each.

The inductor current is indeed continuous, but it suffers a high di/dt at the peaks and troughs.....not as much as say the power switch loop in a flyback which is trapezoidal current though, I would confess. However, it is high di/dt, as in a very short interval of time, the current (at the peak) very suddenly ceases to rise, and then goes down....and that in very very short time.

Also, I am absolutely sure you would agree that current always flows in loops, and the loop responsible for radiating electromagnetic waves is the loop in which the current is flowing in at the time that the radiation is emitted. Electromagnetic radiation is only emitted from the "hot loop" when current flows round that entire "hot loop" (eg the reverse recovery current that I described)

So many thanks for pointing out the "hot loop", however, I would add here that the jist of this thread is that more thermal cooling copper should be used. It is free of charge to use it , because the board area under the inductor is there anyway. You are quite right to warn about adding thermal copper of the switching node...I agree that is a bad idea if drain node copper is splashed all over the place due to its high dv/dt.....however, the discussion here is that there are other copper nodes that could be used as cooling copper which aren't high dv/dt.

I'd always like to just pick a bigger component in order to get extra cooling..but typically, there are always size restrictions, and as you know, one thus needs to maximise what one has got...eg the board area under the inductor.

 

[simonbramble]

I have just slightly re-written the above text to make it easier to understand. I have removed references to the change in area and just focussed on the size of the loop carrying the high di/dts. this makes it easier to understand for future people stumbling on this post.

 

[Flyback]

Thanks, its worth remembering that the power switch loop, comprising the input caps/output caps/inductor/fet carries trapezoidal current....highly discontinuous..... likely to give EMI problems...and this is Aka the power switch loop.
However, the loop that carries any reverse recovery type current as discussed is the worst loop, as the di/dt will be greater.

Of course, that wasn't the thrust of this thread. The thrust is that we electronics workers often suffer small PCB sizes, and should maximise thermal copper pours...the featured app note does not maximise copper pours, and could easily do so, without compromising EMC.

 

[ronv]

It is a pretty conservative thermal design. They probably felt they didn't need them.