VHDL Bit widths and Generics and a counter

[Daniel Wood]

Hi guys. Im quite new to VHDL and I'm trying to design a solution where I can avoid using INTEGERS as much as possible for signals and pin assignments.
Is there any way to determine the length of a bit vector needed from the value of a generic?

For instance if 7 is entered.. A bit width of 3 (0b111) is needed to accommodate it.
If 8 is entered, a bit width of 4 (0b1000) is needed and so on..

Something a bit like...

entity test is
   
    generic (
                x_width  : integer := 1;
                y_width : integer := 6;
                max_count  : integer := 6
            );
               
    port    (    clk :std_logic;       
                x  :in std_logic_vector(x_width-1  downto 0);
                y :out std_logic_vector(y_width-1 downto 0)
            );
end test;

architecture test1 of test is
signal register  :std_logic_vector(reg_width-1 downto 0);
signal count :std_logic_vector(WIDTH_FOR(max_count)-1 downto 0);          --<< THIS LINE

....
....
....

Is there a function or a command like this available? or I could approach using a counter in a different way?

Many Thanks, Dan