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Synching Quartz Master clock to DCF77/MSF

Discussion in 'Electronic Projects Design/Ideas/Reviews' started by oliverb, May 15, 2009.

  1. oliverb

    oliverb Member

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    I have a quartz controlled master clock system that has been up and runnimg now for many years see http://www.electro-tech-online.com/...lock-with-7-seg-led-displays-hourly-ch.18901/ .

    The clock runs fine but the secs need re-synching every few months as they start drifting. I run the clock just a bit fast so after 3 months I just hold the seconds synch button to stop the clock until it is in sync with "atomic time".

    What I want to build is a circuit to keep the seconds in synch from the DCF77 signal. I have chosen the DCF77 as the reciever modules is a bit cheaper £15 rather than £25.

    My initial thoughts are as follows.
    Adjust my master to run just a little slow.
    The DCF77 signal has 58 1 sec pulses followed by a 2sec gap.
    Count the 58 pulses and when the 2 sec gap is detected sync the seconds on my master.

    Looking at Hans Summers site he uses RC networks to seperate the pulses.
    From my very rough diagram enclosed
    I could then have 1 sec pulse stepping IC1. When 58 pulses have been received IC2 goes high. IC3 remains low until the 2 sec (> 1sec) pulse after pulse 58 is detected.

    IC3 going high resets my seconds display (stepping the mins display) and also resets the quartz 1 sec count IC.

    IC1 will also need to be reset (maybe with a slight delay) ready for the first of the 1 sec pulses.

    If and when the radio signal is lost IC3 will not go high and my master clock will drive my clock as normal. The master clock pulse is always just behind the DCF77 will reset IC1 ready to count again when the DCF77 signal returns.


    I have a DCF77 module and have been doing a few experimants and seem to have the 1 sec pulses OK. I will have a play today and see if I can detect the 2 sec pulse reliably.

    I want to keep the project as basic as possible I have no facilties for PICs so am stuck with basic ICs only.

    Any feedback or ideas would be appreciated.

    Thanks.
    Brett.
     

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  2. ericgibbs

    ericgibbs Well-Known Member Most Helpful Member

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    hi Bret,

    Why dont you use the 1 second timing pulses from the DCF77 directly.?

    You could still detect the 2 second break.
     
    Last edited: May 15, 2009
  3. oliverb

    oliverb Member

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    Thanks ericgibbs.
    I did think of using the 1 secs pulse direct from the DCF77 but what if the signal gets lost say at 25 seconds it would not be detected until the the 2 sec pulse at 58 seconds so my clock would stop.

    I suppose I could detect if a 1 sec pulse was not received from 1 to 58 sec then switch back to quartz pulses.

    I think my problem is that there is no "intelligence" in my clock so if I rely on the seconds from the DCF77 I have no way of checking if the display has picked up a few stray pulses due to a noisey signal.
    On a pic controlled clock the display is always updated and correct on receipt of a good 1 min signal.

    This is why I like the idea of the 2 sets of pulses as they can't be used to sync my clock unless both are present after 1 min.
     
  4. dave

    Dave New Member

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  5. dougy83

    dougy83 Well-Known Member

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    Have you had a look at PICAXE chips? They're programmable in BASIC, don't need a programmer (just a cable from your serial port) and they're damn simple (and cheap - 1.73 pound inc. VAT). PICAXE

    You'll be able to filter out dodgey signals ensuring that each pulse has minimum/maximum high/low time, and that the correct number of pulses have been received before syncing your clock.
     
  6. Mr RB

    Mr RB Well-Known Member

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    Very nice master clock, and equally respectable that you did it with logic chips. :)

    Ive been working on a similar master clock for my home automation system, but using a DS32kHz temperature controlled high accuracy oscillator and a car battery so the whole system will never go down.

    One of my future projects will be to sync a GPS module to it, since we don't have radio time standards here in Australia.

    I think your 3 chip system will work, but it would be a shame to have an add-on that could in any way corrupt your clock when your clock is already so accurate. It should be ok if you make sure all the 58 pulses have to be received before the "event", but you still have some issues if a glitch causes an extra pulse? I assume you cause a full reset of the re-sync circuit on the 2 second break?

    It does seem a little clumsy to brute force it to re-sync every minute from a potentially corrupted signal like radio. Maybe you could run a second clock synced to the radio, then check the 2 clocks against each other? That way you can avoid any harsh re-syncing as a single event, but gradually measure the error between the clocks and cause an adjustment?

    That was my proposed plan with the GPS clock sync on my own clock, to measure the error between the GPS clock and my temp-controlled matser clock, then if the per-second error is greater than X for more than 100 seconds (or long period) then make a very fine adjustment to the master clock, to avoid any large re-sync or potentially error re-sync.
     
  7. oliverb

    oliverb Member

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    dougy83 Thanks for that. I will look into them if I can't get it working with logic chips.

    Mr RB Using the 58 pulses and 2 second break should stop any extra pulses from syncing my clock as only a 2 sec break and binary 58 will cause a sync pusle. Looking at my circuit I will have to read all O/P from IC1 not just the 4 shown.
    This will stop it syncing at any other binary number bar 58.

    I will have to reset the sync circuit after the 2 sec break or every min by my master if the radio signal has too many or too few pulses.

    I hope it won't be too harsh as it will only sync a tiny fraction of a second every min.

    There are more details on my master and slave clocks here http://uk.geocities.com/brettoliver@btinternet.com/clock_electronic_1a.htm
     
    Last edited: May 15, 2009
  8. oliverb

    oliverb Member

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    Flip flop config

    I have been doing a bit of thinking about the DCF77 code and have made a few changes to the circuit.

    IC1 counts the 1 sec pulses and via inverts will trigger IC2 only when it has counted 58 times. If there are extra noise pulses or misssing pulses the count will be above or below 58 and IC3 will not trigger.

    IC3 will only trigger when it has received an output from IC2 (count 58) and on receipt of the 2 sec pulse.

    IC3 then resets IC1 and pulses the flip flop IC5. IC5 waits for the next 1 sec pulse before out putting. This output is now exactly at the start of the min.

    If any of the above fails the master clock will reset everything on it's own 1 min pulse.


    I need a bit of help with the flip flop config. I think this is what I need but am not sure how to connect it in this situation.
     

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    Last edited: May 16, 2009
  9. ericgibbs

    ericgibbs Well-Known Member Most Helpful Member

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    hi Bret,
    This image gives most combinations for the 4017.:)
     
  10. oliverb

    oliverb Member

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    Thanks ericgibbs.

    Added a pair of flip flops.

    On IC3 triggering IC5a Q goes high and stays high.
    When the next 1 sec pulse is recieved
    from the DCF77 IC5b Q now goes high sendind a sync pulse to the master clock exactly on the minute.
    IC5a & b are then reset through R1 & C2.


    There is prob a standard diagram for using a pair of flip flops like this so mine is more than likely got some errors in it.
     

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    • Thanks Thanks x 1
  11. dougy83

    dougy83 Well-Known Member

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    I can't see a discharge path for C1.
     
  12. ericgibbs

    ericgibbs Well-Known Member Most Helpful Member

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    hi,
    A point to be aware of, the 4024 is an asynchronous counter[ ripple] and could get 'glitches' on the output of the 4068 which could cause problems in 4027 and RESET lines.

    A simple R/C filter should solve the problem, ideally you should use a synchronous counter in place of the 4024.

    I would suggest you show the 'sense' [ high to low or low to high] of the input and output pulses on the drawing
     
  13. ericgibbs

    ericgibbs Well-Known Member Most Helpful Member

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    hi,
    Isnt the C1 discharge path back thru R1 into 'Q' as 'Q' goes low due to the RESET of the 4027.

    EDIT: my mistake, Im looking at C2.!:eek:
     
    Last edited: May 16, 2009
  14. oliverb

    oliverb Member

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    Do I need Diode D3?
     
  15. oliverb

    oliverb Member

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    Thanks for that. I will bear that in mind before I build it on breadboard. I was going to add alll the details in once I was OK on the basic elements and theory. I'm still not 100% on the type of Logic NAND, AND etc as yet.
     
  16. ericgibbs

    ericgibbs Well-Known Member Most Helpful Member

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    hi,
    With D3, the C1 cap will hold its charge, so IC3 will always see a high.

    Can you post the actual waveforms showing the amplitude and periods coming from the DCF77.
     
  17. oliverb

    oliverb Member

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    Here are some details.
    Will post some more as I find them.
     

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  18. oliverb

    oliverb Member

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    and another.

    I think the amplitude is reduced by 6db for the .1 and .2ms pulses.

    edit. I may well have to put an inverter on the Output from my DCF77 module.
     

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    Last edited: May 16, 2009
  19. ericgibbs

    ericgibbs Well-Known Member Most Helpful Member

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    hi,
    Been looking thru web data ref the DCF signal, from what I have seen and the waveform you have posted the signals
    are not suitable for driving your logic circuit.

    The 2 sec detector that you have adopted is a simple demodulator filter for the received signal.

    You need to demodulate the RX signal and discriminate between the 1sec and 2sec signals which then have to be converted to ic levels.
     
    Last edited: May 16, 2009
  20. oliverb

    oliverb Member

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  21. ericgibbs

    ericgibbs Well-Known Member Most Helpful Member

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    hi,
    Thats better, I see its not just a RXR module.

    I was looking the 77.5KHz carrier'waveforms' that you posted earlier.:)
     
    Last edited: May 16, 2009

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