Switched Capacitor Integrator

[MrAl]

Hi,

Tony:
This has been one of the most confusing issues i have seen in a long time too, i am trying to find out more information on this now. I want to make sure we have the right information to begin with, but i am suspecting now that there is something wrong, almost like Alec suspects now.

Alec:
I think the topology is ok, but there may be something else wrong. I hope not because i spend a decent amount of time on this, but we'll see.

I should have more information in a day or two.

 

[alec_t]

Where did you get the dubious formula?
I've posted another sim over at AAC.

 

[wizard]

Perhaps this sim will help inform the discussion:
View attachment 92548
It is clear from the plot that since C2 = 10 x C1 in this example, it takes 10 steps (10 x the pulse-period) for C2 to charge up to the same voltage that is applied to C1. The output can be deduced as V(out) = -V(in) * (C1/C2) * time/pulse-period.

Hi Alec,

Thank you so much for the simulation...

I think i have a point here,
Here we are going to rech to the gain of the SC integrator with help of the continuse inetgrator as this says:
(0.5* (C2/(C2+C1))* (CONTINUIOUS INTEGRATOR GAIN AT INPUT FREQUENCY)

We want to see if the above formula is correct or not, and so I think we should try to get help from the continuous inetgrator too as the formula we are trying to prove says...

 

[alec_t]

I think we should try to get help from the continuous inetgrator too

The continuous integrator equation is simply V(out) = (-1/RC1)∫V(in)dt, if that helps you?

 

[MrAl]

Hi,

Well in our case i think we are looking for the frequency domain solution, which would be like:
H(jw)=1/(j*w*R*C)

or without considering phase:
H(w)=1/(w*R*C)

and in alternate form:
H(w)=w0/w

and what i had found with the simulations i did was that the switched capacitor integrator had a function:
H(w)=K*(C1/C2)*w0/w, {with K a fixed gain}

and that tells me that the 'new' formula is either wrong or involves some other assumptions or something else we dont know about yet.

My suspicion was that the 'new' formula might be due to using an op amp with finite gain and bandwidth, so i proceeded to come up with a formula for a continuous integrator with that kind of op amp and this is what i found:
Vout=-(Aol*Vin*GBW)/(2*pi*Aol*f*j*C2*GBW*R1+2*
pi*f*j*C2*GBW*R1-2*pi*Aol*f^2*C2*R1+GBW+Aol*f*j)

where
Aol is the finite open loop gain of the op amp,
GBW is the finite gain bandwidth of the op amp,
f is frequency,
j is the imaginary operator,
C2 is the feedback capacitor found in integrators,
R1 is the input resistor of the integrator,
pi=3.14159...

Note that i did not verify this formula yet, but one thing that stands out already and seems intuitive is that any formula that contains a non ideal op amp would have to contain information about those non ideals. This one, as expected, contains the finite open loop gain Aol as well as the finite gain-bandwidth GBW. As far as i know, we cant have a formula without something like these because we would never be able to get the right result without knowing what the non ideals are. This is especially true if we allow the non ideals to change drastically, like 1 to 100000 for example. In this case we'd get different outputs just because that alone, so we'd have to include those i believe.
Now if the good professor is imposing some assumptions that we dont know about, then we'll never be able to figure that out. The only way then is to query the professor for more information. So Wizard, since you got this from the professor you'll have to query him to find out more about this. Perhaps the professor talked about things like this in the past and you forgot.

I had not gone thought the z transform solutions yet mostly because the simulations already had shown the gain is what it is, but we can do that if necessary.
For example, the function then is something like:
(C1/C2)*1/(z-1)

 

[wizard]

Ok Thank you friends for all inputs...

First I invite all of you mates to keep in mind that the "CONTINUOUS INTEGRATOR GAIN AT INPUT FREQUENCY)" in below formula is the gain of the op-amp itself (It is the open loop gain of the op-amp at the input frequency). I am sure for 99% in this regard....
(0.5* (C2/(C2+C1))* (CO NTINUOUS INTEGRATOR GAIN AT INPUT FREQUENCY)

We are going to find the gain of the SC integrator using the continuous one, So we should not leave the continuous op-amp alone and reach to (c1/c2) for the gain of SC integrator while it must be considered too!...
What we are going to do is designing a continuous integrator (by just knowing the input frequency) and finally reach to a SC integrator by replacing the input resistor of the said continuous integrator....
Ok Please let me continue with a real example (which was implemented in hspice too)

A. Designing the continuous integrator:
Suppose we are going to design a continuous integrator at the input frequency of 600kHz...
1. First we consider the C2=1.5 pF (This is an almost attributed/Optional value we select and as you'll see in below is considered to be used for both continuous integrator and SC integrator).
2. Now we find the value of "R" using this formula:
R=1/(Fin*2pi*C2) -> R=1/(600KHz * 2pi * 1.5pF) = 176.84k
So the above formula guaranties to have gain=1 for our continuous integrator we are deigning.
So now we have designed a continuous integrator that has a gain of 1 and we know that it nicely integrates from our input frequency of 600kHz.

B. Ok Now we go for the SC Integrator:

3:We use the below formula to find the value of the "C1":
C1= T/R
Where "T" is the period of sampling/clock frequency (we consider the sampling frequency to be at least 40 times higher than the input frequency --so a sampling frequency of 24MHz is a good choice--).
So C1=1/(24MHz * 176.84k) =0.24pf

Now we have everything we need to design our SC integrator too:
C2=1.5pF
C1=0.24pF
Fin=600kHz
Fclock=24MHz

in such a design the gain of the Sc integrator will be:
(0.5* (C2/(C2+C1))* (CONTINUOUS INTEGRATOR GAIN AT INPUT FREQUENCY)
Were the "CONTINUOUS INTEGRATOR GAIN AT INPUT FREQUENCY" is the open loop gain of our op-amp at the input frequency (ie 600kHz)... The gain of our closed loop continuous --as I designed it above-- is "1", so we "must" be sure that we are considering the open-loop gain of the op-amp at Fin....
You can simulate such a circuit if you like and please keep in mind that the continuous integrator must be considered here as well, as you should be noticed now...

 

[MrAl]

Hello,

Yeah see:
CONTINUOUS INTEGRATOR GAIN AT INPUT FREQUENCY

is a far cry from:
CONTINUOUS INTEGRATOR OPEN LOOP GAIN AT INPUT FREQUENCY

I can not see why anyone, anywhere, with any education level, would state the former when they really mean the latter. Just doesnt make sense to mislead their students that way. That cost us a lot of wasted time and effort. It's almost like we are starting all over again now. Now we are looking for an entirely different mathematical connection than before.

 

[MrAl]

Hello again,

The required "Loop gain" is:
A*s*R1*C2/(s*R1*C2+1)

and i have managed to verify this, however the rest still doesnt fit in.
[Note: The verification is simply an analysis of the op amp with internal gain A, integrator input resistor R1, and integrator feedback cap C2]

If we multiply that by the supposed C2/(C1+C2) then we get:
(s*A*C2^2*R1)/((C2+C1)*(s*C2*R1+1))

and there the only factor missing is the 0.5, which we can leave for later.

Now what the implication is, is that expression is supposed to somehow equal:
1/(s*R*C)

(with the 0.5 factor, so this could really be 2/(s*R*C))

where R is probably R1 and C is probably C2, but good luck equating those two.

This is another one of those error prone problems which you see on the web now and then. I hate working on these kind because you never know what is wrong unless you understand the entire theory and can rework every single equation yourself. I've run into this a number of times even with some well known and pretty smart authors. It takes a lot more time when this happens.

There could still be something we dont know here, but if it is me just missing something somewhere then i have to apologize, buy it looks like you'll have to figure this one out, unless someone else here wants to give it a shot.

 

[alec_t]

Well, I've had my say. I'm convinced the mystery 0.5 and C2/(C1+C2) stem from a different circuit topology than the ones we've considered so far.

 

[MrAl]

Hi Alec,

I have to agree, that something still isnt right. I am tired of working on this problem now

 

[wizard]

Well, I've had my say. I'm convinced the mystery 0.5 and C2/(C1+C2) stem from a different circuit topology than the ones we've considered so far.

Hi Alec,

I revisited your post here:
https://www.electro-tech-online.com/threads/switched-capacitor-integrator.144635/#post-1220905

Sorry but may I ask you to do a favor and modify your simulation so that it satisfies this post as well?:
https://www.electro-tech-online.com/threads/switched-capacitor-integrator.144635/page-2#post-1221486

I guess this way we can be closer to the response we are looking for.

I am also doing a simulation using the Proteus software, but my software gets a problem when I want to run it... I am working to figure the problem out...

Thank you mate.

 

[MrAl]

(somehow got multiple posts, see next post)

 

[MrAl]

(somehow got multiple posts, see next post)

 

[MrAl]

(somehow got multiple posts, see next post)

 

[MrAl]

Hello,

Well 24MHz is a high frequency, which may lead to numerical inaccuracy. I used a much lower frequency when i did the simulation for the actual switching integrator.
You may have to lower the frequencies which doesnt hurt because we only need to see this work at one input frequency, and it doesnt really matter what that is.
As long as you keep the 40 to 1 ratio for clock frequency to input frequency.
I used 100 to 1 for my switch integrator tests so that i could be sure the last two error terms drop out so i'd be looking more at the pure theory than the theory plus error terms.
40 to 1 should be ok too though i guess.

 

[wizard]

Hello,

Well 24MHz is a high frequency, which may lead to numerical inaccuracy. I used a much lower frequency when i did the simulation for the actual switching integrator.
You may have to lower the frequencies which doesnt hurt because we only need to see this work at one input frequency, and it doesnt really matter what that is.
As long as you keep the 40 to 1 ratio for clock frequency to input frequency.
I used 100 to 1 for my switch integrator tests so that i could be sure the last two error terms drop out so i'd be looking more at the pure theory than the theory plus error terms.
40 to 1 should be ok too though i guess.

Well, that example in post #26 was a real example Al, It was implemented in hspice simulator software too and I saw the result (it integrated the sine input accurately and the output was an accurate cosine wave at that freq)....

Well I suggest 40/1 ratio here if possible, so that it satisfies my tests too

Thanks Al.

 

[alec_t]

Keep at it lads! I'm in the Algarve on hol and don't have access to Spice.

 

[MrAl]

For future reference, this is currently post #38.

Hi,

First note that there had been multiple posts in this thread somehow. I can not see how i did not see that before though, so i suspect something is up with the software for the site. It was down for a while yesterday.

In any case, i investigated the hypothesis that the professor meant this:
Gain=LG*0.5*C2/(C1+C2)

where i gave LG earlier in this thread:
LG(s)=A*s*R1*C2/(s*R1*C2+1)

and therefore LG can be expressed as:
LG(jw)=A*(w*C2*R1*(w*C2*R1+j))/(w^2*C2^2*R1^2+1)

and at fixed frequency we can show this as:
LG(jw)=A*(K1+K2*j)

Substituting that into the gain formula we get:
Gain=A*(K1+K2*j)*0.5*C2/(C1+C2)

and lumping the last two factors into K3 we have:
Gain=A*(K1+K2*j)*K3

and allowing K3 to be absorbed into K1 and K2 we can write:
Gain=A*(K1+K2*j)

and this is the expression with fixed frequency and fixed C1 and C2.

The problem is, the gain still changes in proportion to the open loop gain of the op amp 'A', which still can not be correct because for tenfold changes in A we usually see very little change in the gain of an entire stage (assuming A is greater than or equal to say 1000), so this expression doesnt seem to represent the gain of a switched capacitor integrator as proposed.
For example if we set A=1e6 we get a gain G1, and then if we set A=10e6 we get a gain G2 which is equal to G1*10, so the change in stage gain was by a factor of 10 when it should have been closer to 1. Similarly, if we set A=100e6, we get a gain 100 times more than before (with A=1e6), which is not the way the overall stage gain should really change with an increase in the op amp open loop gain.

So the bottom line is there is still something wrong, and it might just be with the interpretation of the professors words, or perhaps the translation to English.

 

[wizard]

Keep at it lads! I'm in the Algarve on hol and don't have access to Spice.

Ok Alec, I see

I finished my first simulation in PSpice software.... I simulated both Continuous and the SC integrators (Please keep in mind that here we are looking for the relationship between the continuous interrogator and the SC one --I'll explain today when I'll add the Schematic and the waveforms of my simulation--)....
The simulation showed to me that the gain of SC integrator I simulated with respect to the Continuous one is "(C2/(C1+C2)" at least for when the gain of the continuous one is 1.

So still I haven't reached to the original formula which Al added here ( ie (0.5* (C2/(C2+C1))* (CONTINUOUS INTEGRATOR GAIN AT INPUT FREQUENCY))... And still I don't know what's the story of that "0.5" there, but Anyway It seems that my result differs somewhat with what you found through your simulation (I mean the "C1/C2" result in your post #10).... I will add the schematic and the simulation waveforms and the math which reaches us from the continuous integrator to the SC one here so that we see what's going on and to have a much better idea about this subject and what i did...

P.S. I must say that the simulation showed to me that the pink part of the formula doesn't refer to the open loop gain of the continuous integrator, but instead it refers to the normal gain of it (ie when the R and C2 are connected, not the open-loop one as it was said to me before!)...

 

[MrAl]

Hello again,

Ok great. Just to be clear, i am getting now from an external source that the 'gain' being referred to here is NOT the open loop gain after all, but is some other gain yet to be disclosed. I think now it is the gain of the RC integrator itself, but we'll see.

Wizard, now that you have simulated the two circuits i would like to see two things:
1. The two circuits and all component values.
2. The two simulation waveforms, one from each circuit at least.
3. How you are reasoning that the two are the same, or are related by that formula in the thread.

Ok that's three things