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STM32F100RB - Basic Timer TIM6

Discussion in 'ARM' started by musselmc, Mar 25, 2012.

  1. musselmc

    musselmc New Member

    Joined:
    Mar 17, 2012
    Messages:
    9
    Likes:
    1
    The problem: For some reason the UIF (update interrupt flag) in the status register goes high before TIM6 overflows (reaches the value in the auto reload register).

    When in debug mode, when I set a break point at the line indicated (then immediately hit continue when stopped) the status register behaves as it should (UIF does not go high until the timer overflows). At first I thought it might be a timing issue, but if I set a reasonably long delay before this line it still doesn't behave as expected.

    Here is my code, in full:

    Code (text):
    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    ; Timer - in ms
    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

    ;Directives
        PRESERVE8
        THUMB

    ;Constants
    INITIAL_MSP EQU 0x20002000  ;initial main stack pointer

    ;TIM6
    TIM6_CR1            EQU 0x40001000
    TIM6_CR2            EQU 0x40001004
    TIM6_DIER   EQU 0x4000100C
    TIM6_SR     EQU 0x40001010
    TIM6_EGR            EQU 0x40001014
    TIM6_CNT            EQU 0x40001024
    TIM6_PSC            EQU 0x40001028
    TIM6_ARR            EQU 0x4000102C

    ;CLOCK
    RCC_APB2ENR EQU 0x40021018  ;Memory for configuring and enabling clock source
    RCC_APB1ENR EQU 0x4002101C

    ;Vector Table Mapped to Address 0 at Reset, Linker requires __Vectors to be exported
        AREA    RESET,DATA,READONLY
        EXPORT  __Vectors

    __Vectors  
        DCD INITIAL_MSP     ;stack pointer at top of RAM
        DCD Reset_Handler   ;reset vector
        DCD nmi_ISR         ;interrupts
        DCD h_fault_ISR
        DCD m_fault_ISR
        DCD b_fault_ISR
        DCD u_fault_ISR

        ALIGN

    ;My program, Linker requires Reset_Handler must be exported
        AREA    LCDDRAFT,CODE,READONLY
        EXPORT  Reset_Handler
        ENTRY

    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    ; Start up code
    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    Reset_Handler   PROC

    clock_init
        ;Enable TIM6 [4]
        ldr R6,=RCC_APB1ENR
        mov R0,#0x0010 ;0000 0000 0001 0000
        str R0,[R6]

    tim6_init
        ;1 clock/ms = 1kHz
        ;PSC = 8Mhz/1kHz - 1 = 7999  
        ldr R6,=TIM6_PSC
        mov R0,#7999
        str R0,[R6]
       
        ldr R6,=TIM6_ARR
        mov R0,#0xFFFF ;count all the way up
        str R0,[R6]

        ldr R6,=TIM6_CR1
        mov R0,#0x0005 ;[bit2]only under/overflow generates interrupt  [bit0]counter enable
        str R0,[R6]

        ldr R6,=TIM6_CNT
        mov R0,#0x0000 ;reset count to 0
        str R0,[R6]

    ;   mov R1,#0xFF
    ;delay
    ;   subs R1,#0x0001
    ;   cmp R1,#0x0000
    ;   bgt delay

        ldr R6,=TIM6_SR
        mov R0,#0x0000
        str R0,[R6] ;clear the status register *BREAKPOINT HERE

        ENDP

    ;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
    ; START OF MAIN PROGRAM
    ;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
    main    PROC

        ldr R5,=TIM6_CNT ;get current count
        ldr R0,[R5]

        ldr R5,=TIM6_SR ;get status register
        ldr R1,[R5]

        b main

        ALIGN
        ENDP

    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    ; Interrupt Handlers
    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
        AREA HANDLERS,CODE,READONLY
        ;default handlers for interrupts and faults
        ;all are infinite loop
    nmi_ISR
        b   .
    h_fault_ISR
        b   .
    m_fault_ISR
        b   .
    b_fault_ISR
        b   .
    u_fault_ISR
        b   .

        END
    Thanks in advance.
     
    Last edited: Mar 26, 2012
  2. musselmc

    musselmc New Member

    Joined:
    Mar 17, 2012
    Messages:
    9
    Likes:
    1
    Sorry guys/gals, the address of RCC_APB1ENR is 0x4002101C, not 0x4000001C, problem solved.
     

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