SpotTheMistake Critiques Roman Black's Two Transistor Switcher Design

[MrAl]

You cannot take the example of a 1.5v battery because the voltage is very low impedance.
In this circuit the impedance is much higher.

The mere fact that the current is changing, means the "back-voltage" produced by the inductor will change.

Hi again,

You're trying to say that the resistance in series with the inductor is much higher so that limits the current, but i covered that case when i mentioned that if the resistance was really that high then the circuit would not oscillate. There's a point there if we gradually increase the resistance it reaches a point where the circuit no longer can start up, and guess what point that is...it's when the transistor can not be forced out of sat by the inductor current rise.

The resistance is quite low, low enough to allow enough current to flow to force Q1 out of sat.

So you really have to point out exactly what you think makes the inductor current stop rising. If you believe it is something else then you have to point it out exactly if you want to convince anyone else. I doubt this will be possible however because simulations verify what myself and others have been saying about this circuit.

The current through the inductor can charge markedly while maintaining a constant voltage across the inductor terminals. That's the way an inductor behaves and that's just basic theory. The equation was given by skyhawk:
v=L*di/dt (with assumed polarity)

Note in this equation that the current has to be a ramp for the voltage to be constant, or the other way around if the voltage is constant then the current will be a ramp. The current is not exponential it is a ramp. It can be a ramp (or very very close to a ramp) because of the short time period we are talking about here which is only part of the full cycle time.
Note that if di/dt changes the voltage wont be constant anymore, but if i is a ramp and only a ramp the voltage will be constant. Since we apply a constant voltage with relatively low impedance the current approximates a ramp very closely.

Do a simulation and look at the inductor current. Note it is a ramp. Also note that the current continues to rise for longer than 200ns after the transistor starts to turn off. If the inductor current stopped all by itself the transistor would still be on and the current would level off rather than reach a sharp peak and then start to fall.
So in the sequence of operation we see the transistor start to turn off, and then some 200ns later the current starts to fall. And we can also note that the current does not level off it reaches a point and then falls with little horizontal portion. There should be a tiny tiny horizontal portion or rather a very small curve (instead of a sharp point at the top) because the transistor can not turn off instantaneously but takes some finite amount of time even with the snap-off feedback of C2. After the tiny downward curve the current then ramps down.
And when exactly does the current start to fall? It falls exactly when the collector voltage passes through the same voltage as the output voltage. As soon as it falls just a tiny bit lower than the output voltage the current starts to fall.

Here is what the two waveforms will look like. Note that the peak of the inductor current is past the point where the collector voltage starts to fall. The collector voltage was hard to draw because it doesnt fall instantaneously but takes some time. The point in time where the peak of the current occurs is the place where the collector voltage passes through 5 volts (the output voltage) on it's way down.
LATER: I added a better diagram below.

   -------   
  |       |<--collector voltage falls here
  |       |
  |       | /\
  |       |/  \ <--inductor current (triangular)
  |       /    \
  |      /|     \
  |     / |      \
  |    /  |       \
--         ---------------> time

Note that the peak of the inductor current is PAST the collector voltage fall point.

 

[colin55]

So you really have to point out exactly what you think makes the inductor current stop rising.

I need to see traces on a dual trace CRO. Not a simulation.
The two transistors turn ON fully and the voltage on the left side of the inductor reaches about 11.5v. At this point in time the transistors cannot turn on any more and the current decreases slightly. This reduces the “back-voltage” produced by the inductor and this is passed to the base of Q2 via the low impedance of the 1n capacitor.
We know the 1n has a voltage change of about 13v and this is passed to the 4n7 to charge it at a rate which is in proportion to their values. That is why the 4n7 is discharged by about 3v.

 

[Mr RB]

Has anybody considered building the circuit and doing a few tests to try and get a better understanding of what may or may not be happening?
...

Hahahaha! YES I designed and built the circuit, and have used for 11 years in many variations, and have spent many hours on the 'scope refining the circuit values and "understanding what is happening", and have spent many emails with others helping them fine tune the circuit to suit their needs also.

Almost no-one understands the intricacies of the operation of the circuit.
One person has already dropped out of the discussion and the other two have incorrect interpretations.
ericgibbs has made statements that don’t make sense. ...

I have an excellent understanding of the operation, and so does Mr_Al whose first post in this thread was practically perfectly in line with my understanding of the circuit. Also EricGibbs has posted an identical analysis complete with simulator results that match all my real world results.

How can the rise in voltage from the output turn Q2 off.

Man this is getting tired. That is the EXACT mechanism of turnoff that I designed. Q2 is the "regulator" and the base of Q2 is held at a fixed 5.6v by the zener, so during the ON cycle, when the outout voltage has finally risen to >5v there is no longer 0.6v B-E required to keep Q2 on and it starts to turn OFF. Positive feedback (C2) does the rest.

The current gets to a maximum due to the two transistors being fully turned ON.

Have you NEVER built a buck SMPS Colin? The current never gets to any "maximum" as the inductor was chosen so that the current ripple remains much smaller than the saturation current where efficiency would be compromised. There is no "current maximum" in regulation and no current sensing as the circuit is voltage regulated.

"It's basic inductor circuit operation where we have a (relatively) constant voltage across an inductor and that causes a continual increase (ramp) in current until something else occurs to stop that increase."
This is entirely incorrect.
How can we have a constant voltage across an inductor and an increasing current through it???

Oh my god. This is the absolute most basic point of a Buck SMPS and most SMPS and inductor theory. When a fixed voltage is applied to an inductor the current rises from zero and the mag field in the inductor increases.

I have been trying to argue some of the finer points of the design like why the C1 energy dump is not "wasted" but it seems you don't even have the faintest clue of how a buck SMPS works, or even how an inductor works?

You say you have been doing this for 40 years but you have never seen "a constant voltage across an inductor and an increasing current through it"?

...However ericgibbs and Mr Al does not understand the intricacies of the operation of the circuit and glosses over the points such as the vital fact that starts the *turn-off* portion of the cycle.

Actually they understand it perfectly, likewise myself. Maybe what they did not understand was the size of the deficit in your electronics knowlege. I'm stunned.

Re closing the thread, I would prefer it not to be closed, at least until Colin has shown some understanding and maybe a correction and an apology if he is man enough. Also the expert contribution (thanks guys!) may help others with an understanding of Buck SMPS design.

 

[JimB]

Hahahaha! YES I designed and built the circuit, and have used for 11 years in many variations, and have spent many hours on the 'scope refining the circuit values and "understanding what is happening", and have spent many emails with others helping them fine tune the circuit to suit their needs also.

Yes I fully realise that this is your circuit, and is an established working design.
I was just thinking that to clarify the operation for the sceptical amongst us, some real world data would be good rather that simulation and theory

JimB

 

[MrAl]

Hi again,

Jim:
It's clear from what colin was saying about the inductor that he doesnt seem to be able to grasp the concept of a constant voltage across an inductor with a ramping current. That alone means that he'll never understand this circuit. He might understand 1000 other circuits but not this one im afraid. And it may not help to build the circuit and measure some points of interest with the scope because some of these waveforms might be hard to see properly on a scope once we zoom in on the turn off time. Maybe not impossible though if MrRB wants to take a stab at doing some scope shots.

colin and others:
Here's another test that can be done to illustrate the way the Q1 transistor turns off...
Using two batteries one 5v and one 9v we'll bias two different points of the circuit to known constant values. Connect the 5v battery across the output of the circuit from the output to ground so that the output is a constant +5v DC. Connect the 9v battery from the collector of Q2 to ground so that the collector is at a constant +9v. These batteries would ideally have 0 ohm impedance.

Then switch on the circuit. What happens?
First, Q1 is biased 'on' but only as much as the resistors R1 and R2 will allow it to be biased on with a 9v drive voltage (the battery). This means Q1 can pass a current through it's collector emitter, and that's what it does. Q1 passes current through it to the left side of the inductor and since the inductor is high impedance over very short time periods initially the collector voltage goes up almost all the way to the 14v power supply rail. Thus the left side of the inductor is at around 13.8 volts, and the right side being biased with the 5v battery is at 5v. So the differential across the inductor is 13.8-5=8.8 volts across the inductor. For the time being that stays constant, so the inductor current starts to ramp up. It ramps up more and more and since it gets that current through the collector of Q1 that means Q1 has to conduct more and more current, but with it's limited base drive it starts to run out of gain so the collector to emitter voltage starts to rise, and that means the collector voltage on the left side of the inductor starts to fall. As the collector voltage falls by 0.8v that brings the inductor voltage down to 8.0v instead of 8.8v but that's only about 10 percent so the inductor current keeps ramping up. The ramp is very slightly less steep now but still the inductor current is increasing because the voltage on the left is higher than the voltage on the right side of it. So we see the transistor stated to turn off yet the inductor current still increases.
Now eventually the collector voltage falls to +5v which is the same as the output voltage. Now the voltage across the inductor is zero volts so the current stops increasing through the inductor. Now since we've disabled the feedbacks the circuit enters into steady state where the inductor current remains constant and the collector voltage remains at +5v.
The timing is such that after about 25us the transistor Q1 starts to turn off and about 200ns later the inductor current peaks. The inductor current stays constant now because the transistor is only partially on with the output stuck at +5v.
So in this case we dont even have any feedback (the 9v battery prevents ALL feedback action from occurring) yet we STILL see Q1 starting to turn off and turning off as much as it possibly can with the load from the inductor drawing current into the 5v battery, and we also see the current again peaking AFTER the transistor begins to turn off, and we also see again the inductor current stop rising when the collector voltage reaches +5v.

That's definite proof of how this circuit works. We broke the feedback loop yet we see the same actions taking place in both Q1 and the inductor. So it should be clear that the inductor current initiates the feedback (along with the slightly rising Vout in the closed loop circuit) and that the current never levels off except AFTER the transistor collector reaches +5v.

colin perhaps you should build the circuit and look for some of these things. One small note here however and that is when you zoom in on the transistor turn off and the current in the inductor, you need to zoom out to see that the current is NOT constant because it only changes a little so it may be hard to view the peak properly when zoomed in. Again, it may LOOK constant when zoomed in but zooming out a little will show the true wave shape. It may take a little fooling around to see it properly on a real scope that's why i drew some pictures.

 

[ericgibbs]

hi Al,

Working on similar line as your post I have simulated this circuit.

Used a 15uS/15uS square pulse drive with the output transistor unused. ie: not driving the inductor.
This is close to the actual circuit frequency.

This enables the inductor current and Q1 emitter/base voltage to be shown relative to the output voltage.

It clearly shows the inductor is never close to saturation, even at the high initial charging current, this is in line with our previous posts.

Eric

 

[colin55]

To put this discussion to bed, once and for all, I decided to build the circuit and squash some of the comments.
Firstly, I changed the 4n7 for 22n. This had no effect on the frequency, so the statement that the author created a timing circuit with the 4n7 and 10k is false.
Then I separated the output with a 1,000u and 4k7 and took the feedback to the emitter of Q2 from this point.
There was no magic pulse present at this point so the statement that the circuit is triggered by a feedback pulse from the output is false. It is purely a voltage reference.
Then I changed the 1.5mH for other values and found the frequency altered. This was due to the inductor saturating and being unable to provide the “back-voltage.” The slight dip in voltage on the collector of Q1 is passed to the base of Q2 via the 1n capacitor.

 

[MrAl]

Hi again,


Eric:
Oh yes that's nice to know too. And we know that if we had an inductor that saturated we would get rid of it anyway and replace it with an inductor that can take the current. So that and your simulation means we dont have to worry about saturation, even in a real life circuit with the correct choice of inductor.

colin:
One point i made with my previous post rather indirectly was that even if the voltage across an inductor is not still constant, as long as there is a still some voltage across it the current will still be increasing. It may no longer be a perfect ramp, but it will still be increasing. This means for our circuit that when the collector voltage is high there is a large voltage across the inductor so the current will be increasing faster, but when the voltage drops as long as the voltage across the inductor still has the same polarity the current will still be increasing. So when the collector voltage is around 14 volts (output 5v) we have 9v across the inductor left side positive we see the current in the inductor increasing, but even if it drops down to 10v (output still 5v) we still have 5v across the inductor with the same polarity (left side positive) so the inductor current still increases just not as quickly.
v=L*di/dt
solving for di/dt we have:
di/dt=v/L
and solving for di:
di=dt*v/L
and from this it is easy to see that the change in current (di/dt) is still the same even if the voltage v drops down lower. To make this really simple lets say L is 1H, then we have:
di=v*dt

That means the change in current is equal to the voltage times the time increment. If the time increment were 1 second we would have:
di=v

which is so simple now. This means that after every second the inductor current increases by the same amount of the voltage. With 1 volt after 1 second we have:
di=1 so i=1
and after another second we have:
di=1 so i=i+1=2
and after another second we have:
di=1 so i=i+1=3
and so on.
Now at 3 amps if the voltage drops to 0.1 volt we have after yet another second:
di=0.1 so i=i+0.1=3.1
and after another second:
di=0.1 so i=i+0.1=3.2
and so on.
It's only when the voltage drops to zero that we have no more change in current even after another second;
di=0 so i=i+0=3.2
and it would stay at 3.2 amps after that unless the voltage dropped negative, then it would start to decrease:
di=-1 so i=i+(-1)=2.2
and so now it drops with time.
That's how simple the inductor operation is.

It gets slightly more complicated when we introduce some series resistance because that makes the response exponential. But with small resistance (as most switching power supplies have) we only see a small deviation from this behavior and it is not enough to change the overall operation. It's only when that resistance gets very abnormally high that we see the oscillator fail but that would again mean we chose the wrong inductor.
Also, with small series resistance and some current still flowing (like at the peak) the point were we see the change come in is when the left side of the inductor is slightly greater than the output voltage because at say 0.1 amps and a seires resistance of 1 ohm we would see the change really start at 5.1 volts instead of 5.0 volts. Still not a heck of a lot of difference.

But colin you still seem to be glossing over the reason why you think that the current levels off rather than continues to rise for at least a short time. You said it was because both transistor are turned on fully and cant turn on any more, but that doesnt cause the current to level off. When Q1 is fully on the inductor current is increasing as any simple simulation would show.

 

[skyhawk]

Here is some analysis for those who can and care to follow the math.

There is an RC timing circuit but the operation is a little more complex. First according to the data sheet a BC337 has a max VCE sat of .7V; therefore, when Q1 is on, point A (the right end of C2) is at approximately 13.3V. After the transient period following Q1 cutoff point A is one diode drop below ground or approximately -0.7V. Thus, during the transient period there is a swing of 14V at point A. This is brought about by a flow of current in C1 and C2. Since C1 and C2 are in series for this operation the same current flows through both. This allows the calculation of the delta V at point Z (the left end of C2). The charge transfer from both capacitors is 14.0*(C1*C2/(C1+C2). Therefore, the delta V at point Z is 14.0*C2/(C1+C2). Plugging in numbers this gives 14.0/5.7 or 2.46V or a potential at point Z of 3.14V, which agrees well with Eric's simulation and also with Roman's measured values (post #33).

During the ramp up during cutoff C1 and C2 are effectively in parallel, so the current charging C1 is ((14.0-Vave)/R)*C1/(C1+C2), where Vave is the average value of the potential at point Z during the ramp up. This gives a dVave/dt of (14.0-Vave)/(R*(C1+C2)). It follows then, that the cutoff time is given by (14.0/(14.0-Vave))*R*C2. Notice this depends on C2 not C1. Letting Vave be 4.0V this gives a cutoff time 14us, which also agrees well with Eric's simulation.

If Colin wants to see a change in timing he needs to vary C2 or R.

It is interesting to note that between the time Q1 cuts off and time the the diode switches on, it is C1 and C2 that are supplying the current to L. The only pulses in the operation are the current pulses in the capacitors when Q1 switches off and again when it switches on. There is no voltage pulse at the right end of L. Quite simply when that point rises above 5V Q2 switches off because the base of Q2 is being held at 5.6V by the Zener, so VBE is insufficient for Q2 to remain on.

Note that in the derivation I neglected the current flow through R during the discharge of C1 and C2 . The formula works reasonably well for this range of parameters, but can give nonsense, e.g. for large values of C2. A more careful analysis is called for.

 

[colin55]

I am not convinced that Q1 has any effect on the timing of the circuit. I changed the 2k7 for 1k5. This will improve the current-handing of Q1. The timing did not alter AT ALL.
I then doubled-up Q1 and the timing remained exactly the same.
I changed the inductor or a higher value and the timing altered appreciably.
This indicates the inductor creates the timing.

 

[Mr RB]

Another good analysis Skyhawk, thank you. However I think there is one error though, you said;

... It follows then, that the cutoff time is given by (14.0/(14.0-Vave))*R*C2. Notice this depends on C2 not C1. Letting Vave be 4.0V this gives a cutoff time 14us, which also agrees well with Eric's simulation.
...

The cutoff time (where the regulator is held off) involves charging of both C1 and C2 together in parallel. C1 contains 3v with it's lower pin at gnd potential, C2 contains 3.6v with it's lower pin at -0.6v.

The RC delay time period must charge both capacitors together until their common voltage >5.6v where the regulator is again enabled.

Maybe I misunderstood your point, but the RC delay period is based on RZ charging both C1+C2 (and obviously plus a small correction as their ground pins are held at slightly different potentials).

To put this discussion to bed, once and for all, I decided to build the circuit and squash some of the comments.
Firstly, I changed the 4n7 for 22n. This had no effect on the frequency, so the statement that the author created a timing circuit with the 4n7 and 10k is false.

This is another situation where you should have consulted the person who has spent many hours examining and tuning the design before making a hasty judgement and going off half cocked Colin.

C1 is discharged by C2. If you increase C1 and don't increase C2, C1 is not discharged as much. Hence it will reach 5.6v quicker when charging via RC. Your test is totally flawed.

The correct way to increase my design's RC delay is to increase C1 and C2 together so that there is still about 45% of the energy in C1 discharged during the turn-off phase and so that C1 ends up at the optimal lower voltage of about 3v. That gives you a comparable voltage in C1 to then be charged via RC during the delay period.

...
Then I changed the 1.5mH for other values and found the frequency altered. This was due to the inductor saturating and being unable to provide the back-voltage.

Sorry Colin, wrong again. The inductor is NEVER saturated. Increasing the inductor size means there is a slower ramping up and down of the inductor current, causing a slower rate of change in load current which causes a slower rate of voltage change in the output filter cap (ie load voltage). As the regulator switches OFF when load voltage>setpoint, it is obvious that a larger inductor will cause some reduction in frequency.

My SMPS design does oscillate around inductor characteristics, with an additional RC time delay during which turn-on is inhibited. It was deliberately designed to model these 2 effects and mimic many of the SMPS driver ICs which also turn OFF when Vout>setpoint and then remain OFF for a fixed RC time delay before the regulator is re-enabled.

In my design the frequency will be reduced for a larger value inductor, and the frequency is also reduced for a larger value RC delay. Both factors have an effect on the frequency.

 

[MrAl]

Hi colin,

To put this discussion to bed, once and for all, I decided to build the circuit and squash some of the comments.
Firstly, I changed the 4n7 for 22n. This had no effect on the frequency, so the statement that the author created a timing circuit with the 4n7 and 10k is false.
Then I separated the output with a 1,000u and 4k7 and took the feedback to the emitter of Q2 from this point.
There was no magic pulse present at this point so the statement that the circuit is triggered by a feedback pulse from the output is false. It is purely a voltage reference.
Then I changed the 1.5mH for other values and found the frequency altered. This was due to the inductor saturating and being unable to provide the “back-voltage.” The slight dip in voltage on the collector of Q1 is passed to the base of Q2 via the 1n capacitor.

As we have said before, if the inductor saturates then it is not the correct choice
for this circuit so get the right value in there and then test again.

I am not convinced that Q1 has any effect on the timing of the circuit. I changed the 2k7 for 1k5. This will improve the current-handing of Q1. The timing did not alter AT ALL.
I then doubled-up Q1 and the timing remained exactly the same.
I changed the inductor for(sic) a higher value and the timing altered appreciably.
This indicates the inductor creates the timing.

No surprise there. I had said that the inductor draws current which draws more current
through the collector and that forces Q1 to start turning off.

I have to commend you highly on the trial test you did (changing R2) which was a very good idea (although it must be altered to see what you are looking for). This kind of test can prove that Q1 pulls out of saturation due to the inductor current rising too high for Q1 to handle, and to try to prove that you were DEFINITELY on the right track!

However, you can not change R2 and expect to see too much change in anything because R2 only slightly changes the BASE CURRENT in Q1 and the base current is the main issue here when you want to test Q1 for turn off when the inductor current rises. To see the change come about in Q1 you need to make sure that whatever resistor you change has a significant effect on the BASE current. R2 does not control this as much as R1 for example. That's because Q2 acts as a sort of constant current for the time we are interested in. It's not perfect so R2 could eventually change the BASE current in Q1, but a better choice is to lower R1. R1 steals base current from Q1 regardless of what Q2 is doing, so changing R1 will have a much more profound effect on the base current of Q1 and thus the collector current point where it gets pulled out of sat. So with this in mind, lower R1 significantly and test again.

You may also wish to look at the base current of Q1 before you do this to verify that what i said is true: that the base current does not vary much when you change R2 from 2.7k to 1.5k or even to 3.5k (plus and minus about 1k). However when you vary R1 you'll see the base current change significantly according to i=0.7/R1 because that is the appoximate current that R1 steals from the base of Q2. As the base current comes down, Q2 will pull out of sat more quickly and you'll see the inductor wave shape change because the peak will be reduced. Since the voltage of the base emitter of Q1 is only 0.7v which is only about 1/10th of the voltage across R2, you'll have to lower R1 quite a bit in order to reduce the base current of Q1. Once the base current (not the collector current of Q2) has been lowered, Q1 should turn off much sooner which means the peak inductor current will be reduced.
It will still operate to some degree because the current still rises and that's what starts Q1 turning off and that's why (as you've noted too now) you see the inductor controlling everything. This will also show that the collector current sensitivity of Q1 plays a major role in the switch off point, and that happens because the inductor current is always on the rise until it shuts off enough for the collector voltage to pass through +5v.

Just keep in mind that you must change the base current of Q1 to see this effect, and that
R2 wont effect this as much as R1 will, and that R1 must be reduced significantly because the voltage across it is small.

We are certainly homing in on the operation of this circuit in more and more detail.
So now that we are homing in on what turns Q1 off, maybe we'll look next at what turns it back on and why and when.

 

[RichTheDude]

To put this discussion to bed, once and for all, I decided to build the circuit and squash some of the comments.
.

So until building the circuit, what was you basing your argument off?

 

[colin55]

I changed the inductor by 10% and got a 10% change in the width of the waveform.
This shows an almost identical response, while changing Q1, doubling up Q1 and altering the base current considerably had NO effect on the waveform.
I think you are wrong with your assessments that Q1 is involved with the timing.

 

[skyhawk]

Eric,

If you still have your simulation available, I would appreciate your running it with values for C2 of 680pF, 1.5nF, and 2.2nF. I have come up with a formula that calculates the delay time as 1.4*C2*RZ, which works well for C2 = 1nF. I am curious to see whether the delay is proportional to C2 as the formula indicates.

Thanks,

Skyhawk

 

[ericgibbs]

Eric,

If you still have your simulation available, I would appreciate your running it with values for C2 of 680pF, 1.5nF, and 2.2nF. I have come up with a formula that calculates the delay time as 1.4*C2*RZ, which works well for C2 = 1nF. I am curious to see whether the delay is proportional to C2 as the formula indicates.

Thanks,

Skyhawk

Hi,
Will do, give me about an hour, will post back

Eric

 

[colin55]

Increasing C2 to 3n3 decreased the frequency slightly.

 

[ericgibbs]

Hi Skyhawk,

These are the 3 sims for C2 cap values of, 680p,1n5 and 2n2.

The file plot names include C2 value for ID.

Same X axis time scale for all three plots.

If you would like further plots just ask.

Eric

EDIT:
Add a composite image of the 3 C2 values.

 

[skyhawk]

Thanks to Eric I have additional data to work with.

I have proposed an equation to compute the off or delay time: 1.4*C2*Rz. Here are my results (second number) with RZ = 10K for various value of C2 compared with Eric's simulator results (last number). For the simulation results I measured the plots off the monitor, so they are sort of rough.

680pF 9.5us 10us
1nF 14.0us 14us
1.5nF 21.0us 21us
2.2nF 30.8us 29us

For those that believe in simulation results (and I do!), I believe that this establishes that the proposed equation is valid. For those who wish to use the equation for other values of Vin, the 1.4 comes from Vin/(Vin-Vave), where Vave is the average value of the potential on the base of Q2 during the ramp up. Vave actually depends on C1 and C2 (details were given in an earlier post) but a value of 4.0 seems to give a good fit over this range of values for the components.

I note that this is a quick and dirty "back of the envelope" approach, but it gives reasonable information to do a design. More accurate results need to take into account the current in Rz during the discharge of C1 and C2 and solve a differential equation rather than using a constant slope ramp up.

It is my opinion that this agreement is sufficient to say that I have a pretty good handle on how the Black Regulator works.

If Colin wishes to see variations in frequency he needs to vary Rz and C2.

 

[colin55]

If Colin wishes to see variations in frequency he needs to vary Rz and C2.

I have already increase C2 from 1n to 3n3 and the frequency changed less than 10%.

I have already told you that changing the inductance by 10% changed the frequency by 10%, so it is the inductance that is having a DIRECT effect on the frequency.