SpotTheMistake Critiques Roman Black's Two Transistor Switcher Design

[Mike - K8LH]

I just spotted a critique of Roman Black's two transistor switch mode power supply design on page 13 of the Talking Electronics Spot The Mistake column. The author attempts to describe the circuit operation because, as he says;

As you can see, arrows on a diagram are misleading and meaningless. The author did not have an understanding of the operation of the circuit and this confused me greatly. I could not follow the operation. That's the purpose of a language. It explains things clearly and accurately.

I wonder if the author tried to email Roman to ask for clarification before publishing the article?

 

[strantor]

I spotted a mistake on that page; the link "Page 11" is shown twice.

EDIT: oh yeah, and the first link to "Page 11" is actually a link to page 1.

 

[PlayNice]

The guy who writes the page has been critized before for his "style" including that there's no way to comment on the page or even contact the guy. Sort of an "I'm right and nobody is going to tell me otherwise" arrangement. Really a class act...not.

 

[Mike - K8LH]

No name calling, please. I just wanted to bring the article to the attention of Roman and the community.

I know very little about electronics so, as far as I know, the author's description of the circuit may be correct. However, I hope everyone would agree the offensive comment at the end of the article was unnecessary, just as offensive comments here are unnecessary.

Cheerful regards, Mike

 

[JimB]

On a slightly different tack, I did notice that one of the circuits on "page 13" was of a battery charger which was the subject of discussion here on ETO in the past week or so.

Look here:
https://www.electro-tech-online.com/threads/basic-battery-monitor-charger-help-me.128701/

It was one of those where you start to think "Why am I doing this? It would be easier to start again with a blank sheet of paper".
Sorry DJAE if you are reading this!

JimB

 

[Mosaic]

Since Mike K8LH appears to be monitoring this particular Talking Electronics Spot, I would ask that he verify his facts before indicating that I am connected with said column.

I link this recent thread where K8LH indicated my alleged connection.

https://www.electro-tech-online.com/threads/pic12f675-software-pwm-led-driver.128364/

 

[Mike - K8LH]

Not sure how that happened Mosaic. My apologies Sir...

 

[Sceadwian]

PlayNice, you mean the full name and phone number on the main site isn't enough? Simply contact Colin, if he didn't write it himself he'd be able to point you to who did.

I've never had a taste for Talking Electronics website. There is very little real design information there, nothing but critique and a collection of slap together often poorly designed circuits using old components. The explanations are often overly simplistic and the site is of little use to understanding electronics, it is however very good for people that just want to throw together something that does something quick and dirty.

 

[Mr RB]

...
I wonder if the author tried to email Roman to ask for clarification before publishing the article?

Thanks for looking out for me Mike and I appreciate you bringing it to my (and everyone's) attention.

No Colin did not contact me for permission or clarification before posting his criticism, however he did have the courtesy to email me afterward saying he had done a critique, and he has met my copyright requirements by posting a link back to my original web page.

I had a bit of a chuckle at his critique as I feel it showed some lack of understanding on his part.

I had just chosen to ignore it, believing my description was fairly accurate and easy to understand.

I'll comment now on his comments;
Phase1; ON
"thin purple arrow is vague". I labelled this as "base current path". This shows the base current from Q1 is not wasted, the base current finds its way to the load.
"yellow arrow is a mystery". It's not a mystery I called it "regulator current path" and true to its name all the current used by the Q2 regulator transistor also finds its way to the load.

Phase2; TURN OFF
"The arrows above are vague and misleading and incorrect".
I think here that Colin shows an ignorance that the "turning off" phase is different to the steady-state "off" phase and/or a total understanding of what I was saying.

The turning off phase involves the discharge of caps. As the buck turns off the inductor pin point A slams below 0v, this causes C1 to discharge and the +ve voltage in C1 to cause a current through C2, as shown by my blue arrow. This current is obviously blocked by the diode, so its path must be through L1 and hence to the load.

All current through RZ cannot be conducted through the zener as point Z is now below the zener voltage, so RZ current likewise contributes to load current (my thin purple arrow).

Phase 2A (colin just made 2A up and scribbled on my diagram)
Here he has said some of the same things i have said above, but in a different way. He still has some misunderstanding of the turn off process;
"At the same time it charges C2 and C1 is discharged slightly". No. C2 is charged slowly during the "off" phase which we talk about next. The "turn off" phase is a transitory phase where C1 energy is dumped through C2 causing the voltage on point Z to drop sharply as C1 energy is dumped through to the load.

This can be seen here on the voltage on point Z (the sharp drop from 5.6v to 3.0v);
**broken link removed**

Obviously that voltage can only drop if energy is dumped out of C1. My diagram for phase2 explains where it goes.

Phase3; OFF (delay period)
"I don't know what is trying to be explained in Phase 3. I don't know what the author means by "Delay Period"... Yep that sums it up. I clearly explained the action of the "off" phase and the delay on my webpage. Maybe Colin did not read it?

It is common in SMPS buck ICs to use a "timed off" period, usually a monostable. I managed to mimic this effect by the combination of C1 and C2 and the energy dump as explained in Phase2. Once C1 has dumped and is at 3v, there is a clearly defined "delay period" while C1 charges again (via RZ) and during this delay period the buck Q1 remains off. This gives a big drop in frequency and improves efficiency for a number of reasons, and also greatly increases stability.

This is also the main difference between my 2tran regulator and Richard Ottosen's original 2tran oscillating regulator. His regulator simply oscillated around a regulating voltage, and was very dependant on load conditions, and was lower in efficiency due to slow switching times and higher frequency.

My regulator provided the "fixed off-time delay period" as used in good buck designs, so it triggers OFF at the regulated output voltage, then has a fixed delay before it can trigger back on. So my design is able to achieve similar performance to a digitally switched Buck SMPS IC as it mimics the very fast switchign times AND the vital "fixed off-time delay period".

I think Colin might not be as familiar with modern Buck designs and had missed this important point entirely.

"C1 is not charged by Rz". C1 is entirely charged by RZ during the "off" phase, unless Colin thinks it is being charged by current out of the base of Q2!!

"and C2 charge-path is not as shown in the diagram above." C2 charge is exacly as I have shown it. As the voltage on C1 rises (due to current through RZ) the voltage on the left pin of C2 must also rise, so RZ supplies current to charge both C1 and C2 during the nice ramp as shown in the 'scope photo above. For C2 to charge during this time, there must be current through C2 which for the reasons I mentioned above current through C2 goes to the load. My diagram is correct.

Phase4 TURN ON
"As you can see, arrows on a diagram are misleading and meaningless." Rather than correct all of Colin's description of this phase, it seems he has an incomplete understanding. The "turn on" is not initiated by a drop in the output as with a setpoint type regulator, because of that critical "delay period" I mentioned the turn on will occur after the delay period when C1 has charged high enough to turn on Q2.

"At the same time C2 charge C1." Correct, but Colin does not understand so is my blue arrow which shows current through C2 into C1 must come through Q1. Also the current surge through C2 causes a higher current pulse into the base of Q2, which can be seen on my 'scope waveform as a "blip" where Q2 base voltage is higher for a short period.

"The yellow base-current path does not pass through R1 but the emitter-base junction of Q1." Finally, a correct critique from Colin. The yellow arrow I correctly called "base current path" but my diagram shows it through R1. In reality with my tested values of R1=1k2 and R2=2k7 there is about 8.4v on R2 =3mA, and 0.6v on R1 = 0.5mA so the "base current path" is 2.5mA from Q1 base and 0.5mA through R1. From memory I called it correctly "base current path" but on the diagram I likely drew the arrow beside R1 to make it less messy. If you check my diagram for Phase1 I drew the base current arrow between R1 and Q1 (as a simplifaction) to show the current really passes through both parts.

"The author did not have an understanding of the operation of the circuit and this confused me greatly." I have no trouble believing that Colin was "confused greatly", but as for me not understanding the operation of my circuit I have hopefully cleared that up in this post.

I'm not exactly sure why Colin wanted to critique my design while barely understanding it, I don't think it really adds to his web page and it does not really affect my web page or the large number of people who have used, understood and tuned my circuit and gained a benefit from it. At this point I think it's some attampt by Colin to add new content to his own page with very little effort on his part and maybe provide cross linking of our two web pages to increase his web traffic. I have not asked him to take down his faulty critique, it does not effect me much and if anything just makes him look bad.

 

[Nigel Goodwin]

Thanks for looking out for me Mike and I appreciate you bringing it to my (and everyone's) attention.

No Colin did not contact me for permission or clarification before posting his criticism, however he did have the courtesy to email me afterward saying he had done a critique, and he has met my copyright requirements by posting a link back to my original web page.

I had a bit of a chuckle at his critique as I feel it showed some lack of understanding on his part.

His posts on here have shown he has only a limited understanding of electronics, but with an inflated opinion of what he knows

 

[karaapak]

I wanna say something not quite interested about the main subject. In one of the forum a guy was trying to find a efficent way to supply his battery operated microcontroller circuit using lcd to show date and time, he was using 7805 to supply 5 V to his circuit and I said to him " you can use Roman Black s 2 transistor Black Regulator Circuit (http://www.romanblack.com/smps/smps.htm)" the circuit you have been talking about, I think they are not interested in how the circuit works but I wanna ask only is Roman Black s circuit more efficent than 7805 as I said to them or am I wrong? In addition to this I wanna thank to Roman Black if he can hear me because I used his 5 V to 13V dc-dc converter circuit in my pic to pic programmer circuit.

 

[Nigel Goodwin]

I wanna say something not quite interested about the main subject. In one of the forum a guy was trying to find a efficent way to supply his battery operated microcontroller circuit using lcd to show date and time, he was using 7805 to supply 5 V to his circuit and I said to him " you can use Roman Black s 2 transistor Black Regulator Circuit (http://www.romanblack.com/smps/smps.htm)" the circuit you have been talking about, I think they are not interested in how the circuit works but I wanna ask only is Roman Black s circuit more efficent than 7805 as I said to them or am I wrong? In addition to this I wanna thank to Roman Black if he can hear me because I used his 5 V to 13V dc-dc converter circuit in my pic to pic programmer circuit.

As a 7805 is as inefficient as it's possible to get, I would hope so

A 7805 is a simple linear regulator, and works by wasting the excess as heat.

 

[RichTheDude]

Critiquing peoples work is a good thing, but it should be done in a respectful manner (i.e. not publicy stating the author “knows nothing”) and in my opinion it should always be discussed with the original author, with the authors permission being gained for publication.

I decided to have a look at Colin’s website. I picked a design at random to get a feel of the website and the designs. I picked this one: http://www.talkingelectronics.com/projects/ThrottleMkI/Throttle.html
Teaching beginners that paralleling diodes is in my opinion bad, and is a bit of a cowboy trick to do, they may do the same with diodes which have less forgiving Vf temperature profiles.

 

[3v0]

It boils down to attitude. Decent people try to be helpful, the rest get their jollies out of degrading others.

 

[colin55]

The "turn off" phase is a transitory phase where C1 energy is dumped through C2 causing the voltage on point Z to drop sharply as C1 energy is dumped through to the load.

This is incorrect. The energy is not passed to the load as the right hand end of C1 is connected to the cathode of the high-speed diode and it is CONDUCTING during this part of the cycle and the energy from C1 is being LOST.
The right hand side of C1 is changing from +5v to -0.5v and the ratio of the 1n to 4n7 creates a lower voltage on the join of the two capacitors.

 

[Mr RB]

To NigelGoodwin and 3V0; yeah I'm not angry at Colin nor did I think he was deliberately malicious. I don't think that it was his intention to cause harm, it looks to me like his intention was to add content to his page with very little effort or care on his part and to probably to try to use my SMPS page link (which has been up for years and is very well google linked) to bump his own webpage hits up. He's done similar things to "critique" other people's web pages as we've all seen. This month it was my turn.

To Karaapak; Thanks for the compliment. Regarding my 2-tran SMPS efficiency, my page has a chart showing efficiency of the SMPS from 14v in to 5v out at 70-80%, so;

7805; 14v 33mA in, 5v 25mA out (uses 33mA from the input)
My SMPS; (at 76% eff) 14v 11.4mA in, 5v 25mA out

So the 7805 would consume almost 3 times more current from the battery as the 2-tran SMPS. With a battery at 12v in, it would be slightly less efficient but still about 2.5 times better than a 7805.

 

[Mr RB]

This is incorrect. The energy is not passed to the load as the right hand end of C1 is connected to the cathode of the high-speed diode and it is CONDUCTING during this part of the cycle and the energy from C1 is being LOST.
...

Well maybe I am wrong Colin regarding where the current goes when C1 dumps from 5.6v to 3.0v. I welcome your input and would like to discuss this further until we can work it out for sure.

I just whipped up 3 diagrams, see below;

In diagram 1 it shows the Buck mode, where the transistors have turned off at a point where there was 1A of inductor current. At this point the inductor continues providing 1A of forward current through the load, in a loop consisting of inductor+load+diode. The entire load current of 1A is being supplied from the energy stored in the inductor.

**broken link removed**

In diagram 2 it shows that C1 is acting as a current source, and supplying 0.5A into point A, this is comparable to what we are discussing.

To my judgement, if C1 is suddenly supplying 0.5A the inductor field will remain fairly constant at 1A, with load at 1A, however the "Buck effect" is now only taking 0.5A supplied from the collapsing mag field of the inductor. So to my thinking, C1 current of 0.5A is being supplied into the load, AND there is less energy taken from the indutor to suit.

If you check diagram 3, as an example if at this point in time C1 was supplying 1A, this goes into point A, and inductor current and load current remains at 1A, but there will be no buck diode current and no energy drawn from the inductor, whose magnetic field will remain constant. In that case the entire 1A of load current is being supplied by C1.

I would really appreciate any expert opinion on this (Mr_Al? Nigel?) as if this is not correct then I would like to make the correction on the diagrams on my web page.

 

[colin55]

Firstly you are changing the whole circuit.

C1 is not connected to the inductor.
I have added a lot more discussion on my web page as you have brought up a lot of new inaccuracies and some of them have been addressed.

To take the circuit above, that you are trying to explain, I will provide an explanation.
The concept of an inductor trying to continue to keep the current flowing after the voltage is switched off is causing you all the problems in the world. It is like a bank putting $1,000 into your mortgage each week after you cannot make the payments.
In circuit No1, you cannot work on CURRENT values. You have to work on VOLTAGE values.
This is because the inductor produces a VOLTAGE in the opposite direction when the current flowing through it is REDUCED.
When the current is reduced to zero at a very quick rate, the voltage produced by the inductor is very high. It may be 10 times the original voltage across the inductor or it may be 100 times higher. The ratio does not matter. The only thing that matters is the fact that when the voltage across it is 5.6v, the right hand end of the inductor is at 5v, and the left end flips the high-speed diode over and it is turned up-side-down and has -0.6v on the cathode.
Your diagrams 2 and 3 are meaningless and incorrect as C1 has all its energy cancelled by the energy from the inductor, if it is a small value. If the energy from the inductor is not sufficient to cancel that from C1, then C1 adds to the energy from the inductor and this energy is passed to the load.
However this is not the case with the 2-transistor buck design as the closest cap to the inductor is 1n and it is in series with 4n7.
If you say the voltage on the base dips by about 3v, the right lead of the 1n is being taken to -0.6v.

 

[Mr RB]

Firstly you are changing the whole circuit.

C1 is not connected to the inductor.
...

I have not "changed the whole circuit". Your sole point in post #15 is that the energy supplied from C1 when it discharges from 5.6v to 3v is "lost" as it goes through the diode.

I have drawn this issue in a simplified form, removing C2 as it is not relevant to the argument. The current from C1 is supplied into point A (the join of the inductor and diode). This is a fact.

...
To take the circuit above, that you are trying to explain, I will provide an explanation.
The concept of an inductor trying to continue to keep the current flowing after the voltage is switched off is causing you all the problems in the world.

I don't have "all the problems in the world". I have a good understanding of Buck topology.

...
In circuit No1, you cannot work on CURRENT values. You have to work on VOLTAGE values.

This is where YOU have the problem. I know exactly what the voltages are doing, and I know why the voltages are largely irrelevant. The buck current path is clearly understood.

...
The only thing that matters is the fact that when the voltage across it is 5.6v, the right hand end of the inductor is at 5v, and the left end flips the high-speed diode over and it is turned up-side-down and has -0.6v on the cathode.

I always understood that, and again it is irrelevant. The Buck loop of inductor/load/diode form a CURRENT process and when you say "the only thing that matters is the voltage" it makes you look very ignorant.

...
Your diagrams 2 and 3 are meaningless and incorrect as C1 has all its energy cancelled by the energy from the inductor...

Proof is necessary Colin, if you want to be taken seriously. I have posted details of the relevant currents in the 3 diagrams above.

...
I have added a lot more discussion on my web page as you have brought up a lot of new inaccuracies and some of them have been addressed.

Looks like you are digging an even bigger hole for yourself continuing to criticise without understanding what you are talking about.

Here is an example from your new content;

"Roman is mixing up the defined "timed off" period in a buck IC circuit with the 2-transistor circuit above. The capacitors C1 and C2 have no effect on the frequency. The frequency is generated by the time it takes to release the energy from the inductor during the "turn off" period."

You still have not grasped what I have explained on my web page and again explained in detail in this thread. Once C1 is discharged to 3v, there is a RC time delay formed by RZ and C1, and the transistors CANNOT be turned on again until the RC delay charges C1 to again reach 5.6v. This has NOTHING to do with the inductor characteristics but is a very separate RC delay that does indeed reduce the switching speed of the SMPS. It's ridiculous statements like these that you keep making that are destroying any credibility that your argument may have.

Please discuss my proofs as posted in #17 diagrams. When the transistors turn off, there is a buck current as shown of 1A through the buck loop; inductor/load/diode. This is a fact. When C1 discharges from 5.6v to 3v through C2 it releases its stored energy, and delivers current into point A. This is another fact.

Any current delivered into point A when the buck cycle is happening contributes to buck current and reduces the energy drawn from the inductor. Indeed, if the current into point A equals the buck current the inductor field will remain constant and there will be no energy drained from the inductor.

 

[colin55]

The amount of energy coming from the 4n7 and 1n is miniscule.
Diagram 2A on my website shows the high-speed diode flipped-over and the energy from the collapsing magnetic field of the inductor provides all of the energy during this part of the cycle.
This right-hand end of the 1n is pulled down from 5v to -0.6v by the action of the inductor and this capacitor is almost uncharged at the beginning of the cycle. It gets charged by the 4n7 and 10k resistor but there is no "pressure" from the 4n7. The 1n actually “sucks the 4n7 down” rather than the 4n7 charging the 1n.
The timing comes from the inductor. The 4n7 is discharged and charged by the action of the inductor and 1n, to a much greater extent than the 10k resistor. The impedance (capacitive reactance) of the 1n at 100kHz is only a few ohms as compared with the effect of the 10k resistor. It merely "tops up" the 4n7 and 1n so the transistor will turn on hard during the next part of the cycle.
The 4n7 has only a few volts “to do any work” and certainly does not provide any energy to the output.
The 1n has a much greater effect on charging the 4n7 than the 10k, so the delay you are talking about with the 10k and 4n7 does not exist.