Rising edge detector

[shortbus=]

I need a edge detector circuit for clocking a 4013 flip flop. Googled and checked the books I have but many of the circuits shown are slightly different and they often show the same circuit but contradict themselves in the explanation of them. I need one that take a digital level high and out put a short high pulse then return to digital low. I'm new to logic circuits and could use some help with this.

 

[MikeMl]

The 4013 already clocks on the rising edge. It clock input can stay high for a week, and then go low just long enough to meet the setup time to catch the next clock edge. Why do you think you need to "shorten" the logic level high time?

 

[Tony Stewart]

A double edge detector is an XOR gate with a short RC delay in one path.

A single edge one shot is just a diode clamped differentiator into gate input or a precision dual one shot chip in HCMOS.

 

[shortbus=]

The 4013 already clocks on the rising edge. It clock input can stay high for a week, and then go low just long enough to meet the setup time to catch the next clock edge. Why do you think you need to "shorten" the logic level high time?

Thanks Mike. I didn't know that, like I said in first post I'm new to this. I was under the assumption that a edge detector had to be added, didn't know one was built in to the clock input. Since there are so many shown in the books/online just thought it was some thing needed.

Next question on the 4013, and due to the unavoidable electronic noise in this project I think the 4xxx logic is needed. Can two different signals be used on the clock? I'm using this to time the turn on off of a mosfet. Both signals will be from voltage comparators, when a certain voltage is reached a mosfet will be turned on. when the next voltage level is reached that mosfet needs to be turned off. I would diode "or" the comparator outputs before the 4013 clock. The 4013 is just to being used as an electronic SPST toggle switch basically.

 

[Tony Stewart]

You can get better noise immunity on Atmel type CMOS at 3.3Vwhich has 25Ω drivers., whereas HCmos is 10x this amount Ranging from 250 to 200Ω from 15 to 10V. There are over 20 CMOS family extensions for speed, ESR or current ratings and voltage range.

But the trick is to employ LC filters and Schmitt Trigger input buffers with termination pullup/down Rs to match your cable impedance biased at midpoint threshold with an effective input load of say 250 to 500 Ω . .e.g. 1k pullup //1k thus drop at driver is 5-10% of unloaded swing but noise suppression from stray capacitance on E fields or stray inductance from currents causing H field impulse are attenuated by impedance ratio of stray to signal. CM choke on radiating source help as do ferrite beads for high impedance inputs, and bigger beads for terminated inputs.

standard 5V logic with buffered outputs may be in the range of 50Ω.


Also beware FF's can toggle their outputs from EMI coupling to outputs so buffering is preferred with CM beads on long lines.

Anything can be made to work, but immunity varies by noise current or voltage and low controlled impedance for differential and high common mode impedance must be understood for best performance.

 

[Reloadron]

Hi Ya Shortbus, I believe you are planning to have these positive going pulses come from your comparator level detector circuits, would that be correct? No, as Mike pointed out there is no need for any edge detector circuitry as the 4013 will clock fine on a rising edge. What I am not quite understanding between this and a previous thread is why the 4013 D flip flop in here?

Ron

 

[shortbus=]

Hi ya back, Ron. I decided to ask here because my thread on rising edges at AAC got me in an argument. I'm the first to admit my lack of understanding about this stuff, but still don't get what I was being told there about it's better to use set and reset than to use the clock terminal?

I was always planing on the 4013F/F . Didn't realize it had a built in edge detector. But still having trouble understanding if two different high signals can be used as a clock one after the other. Will the second one be recognized when there is already one present? Or do they both need to be made into a pulse? There needs to be two independent clock inputs to toggle 'on' then 'off'.

What I'm hoping to accomplish out of the use of the F/F's is to use voltage comparators in different areas of the circuit to then turn on and off other parts of the circuit. Can't really see why it won't work because the whole machine is about charging, storing and discharging voltage in a cap bank.

 

[Reloadron]

I was always planing on the 4013F/F . Didn't realize it had a built in edge detector. But still having trouble understanding if two different high signals can be used as a clock one after the other. Will the second one be recognized when there is already one present? Or do they both need to be made into a pulse? There needs to be two independent clock inputs to toggle 'on' then 'off'.

I believe it was Alec who did the drawing using a few clocks diode coupled to a CD4013 D Flip Flop. The 4013 will trigger and change output states on a positive going edge. If that signal is High and another High comes along nothing happens. Here is another example:

V1 and V2 are clock pulses, 1 second on and 1 second off for simplicity. Clock V2 has a 0.5 second delay with respect to Clock V1, this can be seen in the two top traces, V1 and V2 respectively. Vclk is what actually goes into the CD4013 Flip Flop after the blocking diodes. Note the ON time of Vclk. If V1 or V2 is High then Vclk will be High. There is another caveat to all of this in that the CD4013 set up this way is a /2. If you actually look at Vclk the Vout is Vclk/2. Two pulses in and one pulse out or divide by two.

Something you may want to try is looking at your big picture. For example, look at everywhere you plan to maybe use a comparator circuit and then list what you want to do with that comparator signal.

Also, everyone is aware that just about all of this stuff is new to you so don't let not having an understanding of any of this stuff bother you in the least. I can appreciate it is hard to express things in an area you are just learning, right down to the terminology.

Ron

 

[alec_t]

I believe it was Alec who did the drawing using a few clocks diode coupled to a CD4013 D Flip Flop.

I did show how two clock sources could be diode OR-ed, but made no mention of their timing. I was not aware then that one source going high while the other source was already high might be a problem. That situation might require some sort of negotiation/prioritisation, depending on the intended circuit function. As you recognise, turning each source signal into a brief pulse could be the answer, since it would drastically reduce the chances of two signals overlapping.
But if, say, the latch is already set when two incoming pulses coincide, both are clearly intended to reset the latch, so does it matter which one causes the reset?

 

[Reloadron]

I did show how two clock sources could be diode OR-ed, but made no mention of their timing. I was not aware then that one source going high while the other source was already high might be a problem. That situation might require some sort of negotiation/prioritisation, depending on the intended circuit function. As you recognise, turning each source signal into a brief pulse could be the answer, since it would drastically reduce the chances of two signals overlapping.
But if, say, the latch is already set when two incoming pulses coincide, both are clearly intended to reset the latch, so does it matter which one causes the reset?

Hi Alec, while I have some ideas as to where all of this is going, I am not 100% sure what each building block will need to do. Thus my suggestion to get everything, each block on paper and define what each block does. Then the sub-circuits and their logic can be worked out. That is pretty much my thinking on it anyway. Shortbus is into a pretty good project but it will likely take some doing and he will need some help.

Ron

 

[shortbus=]

Hi, Ron and Alec, thanks for understanding an old dummy. I was OK until brownout through me a curve about not using the clock for a clocked flip flop. But in a round about way he helped me (don't think it was intended though, he's told me numerous time my ideas won't work), then someone else says they will. I'm pretty sure if instead of the diode 'or' I wire a pair of 'and' gates to the Q and not Q of the flip flop, and put my signal from the comparators into the other inputs on the "and" it will only give a clock to the clock pin one at a time. What I'm trying to say is, if Q is high and the signal from the comparator wired to that 'and' is also goes high, a clock signal should go through. Nothing bad will happen if the 'and' that's off output has a high will it?

Just for my own knowledge, isn't it better to use the clock when available instead of S or R to make the flip flop do it's thing? The way I understand it is S and R are for startup or preloading the output. Or was he correct?

I'm not counting or dividing a set of pulses, just want to use the 4013 set up as a "T" to turn on and off a mosfet at a certain volt level from the comparators. Thanks again for the help and interest in my project.

 

[Reloadron]

What I'm trying to say is, if Q is high and the signal from the comparator wired to that 'and' is also goes high, a clock signal should go through. Nothing bad will happen if the 'and' that's off output has a high will it?

What you are getting at here is along the lines of a Pulse Steering Circuit or what I call steering logic. Let's use the motor up / down thing as an example since it uses comparators.

Well, OK, I screwed up and lost my color. Saving the image grey scale was not my best move.

Vsig in this case (top trace) is just a 0 to 5 volt signal over a 5 second period. It repeats twice in the 10 second sweep. TP2 and TP3 are the outputs of two adjustable comparators which form a window. When Vsig is within the window both comparator outputs are High. The comparator outputs run to a few three input NAND gates which form a steering circuit for the clock pulses from the 555. When either output of a comparator goes Low the clock pulses are "steered" to TP4 or TP5. So I have either no clock pulses out or clock pulses on TP4 or TP5. Note how when TP2 and TP3 are both high neither TP4 or TP5 have any output clock pulses. This only happens when Vsig is within the window set by the comparators. Does that make sense to you?

Again sorry about the grey scale (black and white) image.

Ron

 

[ChrisP58]

I suggest making up a state table. Show all your inputs, including transitions, and the resulting outputs you want. Then you can match the logic up to your needs.

 

[alec_t]

Both signals will be from voltage comparators, when a certain voltage is reached a mosfet will be turned on. when the next voltage level is reached that mosfet needs to be turned off.

Starting with this requirement, do you even need a 4013 latch? Just a window comparator or an XOR gate would seem to provide the necessary logic, unless the comparators have no hysteresis and give jittery outputs. Or am I missing something?

 

[Reloadron]

Starting with this requirement, do you even need a 4013 latch? Just a window comparator or an XOR gate would seem to provide the necessary logic, unless the comparators have no hysteresis and give jittery outputs. Or am I missing something?

Nope, not missing anything, that's about it for one block. The circuit above looks at a voltage level. If the level increases a comparator sends a signal state to have a motor run in, if the voltage level decreases a comparator sends a signal and we want the motor to run out. Which way a streaming clock pulse is routed is the end result. When the sensed voltage is between two set levels nothing happens. No need for a flip flop in this example.

Ron

 

[Tony Stewart]

Realize that signal integrity is a serious concern on long wires. Impedance of UTP, capacitance per foot, termination impedance to threshold voltage like 1.2V with pullup/down R's , RF caps, CM chokes and shielding , single ended and RS485 are all tools to ensure integrity of the interface. Edge sensitive asynchronous protocols are inherently worse than centre sampled (RS232) and high speed integrity needs to be defined in error rates, and noise levels expected.

Welcome to the Analog World of digital Signal Integrity.

 

[shortbus=]

Thanks everyone for the help. I'll up load the simple block diagram of what needs to happen, it is step by step. And a equally simple timing diagram with a low quality schematic of the proposed circuit. I didn't draw the parts in the correct way I know, it was just for a kind of "shorthand" schematic showing the major parts needed. I'm still drawing "kindergarten" stick figures compared to you guy's masterpieces.

 

[Tony Stewart]

This wont work as fet sources are diode or's are connected to a floating gap,.
You need a high voltage pulse from coil to gap to breakdown 3kV/mm then when avalanche occurs, storage caps will be shorted out, resulting in a burning detonation and vaporized contacts unless tungsten golf tees or spark plug. Even these will wear out faster than a car.

Dont you want to stretch the duration of the discharge? Then big LC resonant circuit can be used or variable reluctance gapped arc welder transformer.

Ipk , T50 duration and Energy levels do you expect? Holding current? Discharge voltage, inrush current limiter? ESR of caps? rdsOn of FET?

 

[Tony Stewart]

How did you expect this work? Magic?
Is this just a dragging spot welder? If so N.G.

At 1kV/mm 117Vdc will arc with a gap of 0.117 mm maybe...

 

[ronv]

It's an EDM machine.