MOSFET circuit question

[earckens]

ok, thks. I am working on an Eagle schematic in will post it the coming days.
Grts,
Erik

 

[MikeMl]

To MikeMI: what is Ix (yellow) in your graph? You omit D2 and D3?

The yellow trace is the relay coil current. The gray trace is the current through the snubber diode. They are equal between 57ms and 90ms. Note that the inductance of the relay coil is what determines the rise and fall time of the coil current. I never met a "power" relay that operates in less than about 25ms. V(out) shows when the relay contacts close/open.

A 2N2222 will tolerate a max base current of up to ~80mA @ a Vbe of ~+1V. The max voltage across the burden resistor to approach 80mA into the base would be 1+1000*0.08 = 81V, so I dispute that you need D2/D3. Note that I moved D1 downstream of the 1K resistor so that -Vbe gets clamped to ~-1V without upsetting the burden resistor voltage..

Here is a detail of the voltages and currents at the input of Q1 based on a reasonable guess of leakage inductance of a 20kHz Current Transformer:

 

[earckens]

Hi MikeMI: impressive! What program do you use for this simulation?

I will make an inverted diagram with a pnp and n-channel i.s.o. an npn as now. As sson as ready I will post it here.

To get TTL output, I think a 4.7 or 5.1V zener with a 2k series resistor between the Q1 collector and ground will upset the C1 functioning. What would you suggest for this addition?

 

[MikeMl]

Hi MikeMI: impressive! What program do you use for this simulation?

I will make an inverted diagram with a pnp and n-channel i.s.o. an npn as now. As sson as ready I will post it here.

To get TTL output, I think a 4.7 or 5.1V zener with a 2k series resistor between the Q1 collector and ground will upset the C1 functioning. What would you suggest for this addition?

LTSpice.

Do you want the TTL output at the same time as a relay output, or instead of...?

I could see a 5V version for TTL output, or possibly using a 5V relay at the same time as making a TTL output powered from 5V. You will have to use logic-level NFet for a 5V only version.

 

[earckens]

TTL output preferably at the same time as the relay output; a separate simultaneous output, to an MCU for example.

 

[AnalogKid]

Here is the upside down version, with a TTL output, plus a little hysteresis (R5). to keep the relay from chattering on release.

ak

 

[MikeMl]

It occurred to me that the way the transistor is used, it is a "peak" detector. As such, it will respond to even a PWM signal with a very small duty cycle such as 1% or 2%. You might be better served by a detector that responds to the "average" of the PWM signal, such that it is off for less than say 10% duty cycle, and on for more than 10%. To do that, the detector would have to be more of a Low Pass Filter followed by a comparitor.

 

[earckens]

To AnalogKid: thank you for this diagram!
Just a few questions:
1. why R3?
2. why not eliminate Q3 and connect zener D3 with load resistor R4 in series to Q1-collector?

EDIT: 3. is there a way to convert 4 channels from Vcc to TTL? Preferably with an IC so that I can reduce cost and space?


To MikeMI: fair proposition; but I am not sure whether I only want to detect pwm signals: T1 serves to detect "any" current going through the primary, therefor the design as-is might well serve its purpose. I am so sorry for this confusion but I am still in the process of discovering the DCC signals used for model railroading. The purpose of this design is to detect whether there is any model locomotive on the track at all, so any current -pwm or not- should be detected.
And I think pwm is only part of the DCC signal. I know, this seems like designing circuits without knowing all prerequisites but sometimes I get taken away by enthusiasm before knowledge

 

[MikeMl]

Here is the upside down version, ...

I suggest that a burden resistor be connected across the CT secondary. It becomes the transducer that converts primary current to a secondary voltage...

 

[MikeMl]

... I know, this seems like designing circuits without knowing all prerequisites but sometimes I get taken away by enthusiasm before knowledge

I would connect your proposed CT (with a suitable burden resistor) to your layout. Use an o'scope to view the signal across the burden resistor. Post a picture if you have the ability...

 

[earckens]

To MikeMI: next week I might have the capability to take and post a picture.

To AnalogKid: for the TTL output, why not use a voltage divider resistor set of about 2k instead of D3, Q3 and R4? The input impedance of the load (an MCU) is 10k.

 

[AnalogKid]

why R3?

Because Mike added it. I think it can be eliminated.

why not eliminate Q3 and connect zener D3 with load resistor R4 in series to Q1-collector?

Because I focused on a semi-isolated TTL output. Your suggestions is better.

To AnalogKid: for the TTL output, why not use a voltage divider resistor set of about 2k instead of D3, Q3 and R4?

The zener gives a constant output voltage over a range of currents from 0 to around 7 mA.

ak

 

[MikeMl]

Because Mike added it. I think it can be eliminated.

I put the R2/R3 voltage divider there to control the peak gate voltage on the PFET. If running on 12Vdc, without R3, the peak Vgs would approach the supply voltage. That may or may not be ok depending on the PFET.

 

[AnalogKid]

Here is a reworked version.

ak

 

[earckens]

Because Mike added it. I think it can be eliminated.

Because I focused on a semi-isolated TTL output. Your suggestions is better.

The zener gives a constant output voltage over a range of currents from 0 to around 7 mA.

ak

ok, thank you! Your suggestions will be applied.

 

[earckens]

I put the R2/R3 voltage divider there to control the peak gate voltage on the PFET. If running on 12Vdc, without R3, the peak Vgs would approach the supply voltage. That may or may not be ok depending on the PFET.

ok, thanks MikeMI; I think of using FQP30N06L because I have it lying around.

 

[earckens]

I would connect your proposed CT (with a suitable burden resistor) to your layout. Use an o'scope to view the signal across the burden resistor. Post a picture if you have the ability...

Hi Mike, here is some clarification stating the actual square wave signal (the one I want measured throught the current transformer) has half periods of 58µs for 1 and 100µs for 0 meaning 1/(2 x 0.000058)=8,6KHz to 1/(2 x 0.0001)=5kHz frequency: https://www.dccwiki.com/DCC_Power

 

[AnalogKid]

A lot less than 20 kHz (post #1) but not enough to matter.

ak

 

[earckens]

A lot less than 20 kHz (post #1) but not enough to matter.

ak

I know. Next time I will be better prepared before posting. For example https://www.electro-tech-online.com/threads/optical-4-ch-ldr-object-detection.150999/

 

[earckens]

Here is a reworked version.

ak
View attachment 106153

I hit an issue with this design: if I want an open collector digital output (referred to here as TTL output), I think I have to use an NPN for Q1; and thus a p-channel OSFET for Q2.
Or add a NPN with OC?
What do you suggest?