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Matching NFETs?

Discussion in 'General Electronics Chat' started by Mosaic, Mar 22, 2017.

  1. schmitt trigger

    schmitt trigger Active Member

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    Nice trick!

    I also agree with Shortbus......for very high power applications, one requires some real "muscle".
    ISOTOP is an STMicro trademark. Other companies offer similar products. The actual JEDEC designation for that package is SOT227B.

    Ixys, Infineon and other make them.
     
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  2. tomizett

    tomizett Active Member

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    Good detective work Mosaic, looks like you may have found the problem. I suppose this points to a higher-than-expected stray inductance in the system - at such high currents, even a small inducance must mean quite a large amount of stored energy.

    Although the others have a point about the advantages of using rather more exotic heavy-duty FETs for an aplication like this, personally I have a lot of respect for the designs that manage to squeeze "unexpected" preformance from everyday parts.
    On a practical note, it may be more economical to use several smaller devices - especially if you do start destroying those massive FETs!
     
  3. Mosaic

    Mosaic Well-Known Member

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    Well it's the current being so high (400A) charging the inductance . At .023 J per pulse of back emf the parastic inductance is only 300nH. Multiply that 700+ times per sec. and dissipation becomes significant.

    The big industrial FETs seem to be less able to handle pulse current spikes than the ones I am using and better at large continuous currents. Also the units I see are many times the price range of 4 IRFP3206 and don't meet the RdsOn spec (1 mΩ)or Pulse current capability (>800A).
     
  4. dave

    Dave New Member

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  5. schmitt trigger

    schmitt trigger Active Member

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    There are many ways to skin a cat.

    I have seen several of Mosaic's posts and know he is a *very* knowledgeable fellow.

    But I was advising about the larger, single unit FET because there is an IR app somewhere, where they discuss the fact that nanohenry differences in the stray inductance among devices would cause huge thermal differences across paralleled devices.
    Since the app note was written by a semiconductor company, they actually had batches of "naked" FETs (without the epoxy moulding). With a FLIR camera, one could see the die temperatures across all paralleled FETs.

    At low switching frequencies, the temperature delta was insignificant. But as frequency increased, the delta became noticeable.
     
  6. Mosaic

    Mosaic Well-Known Member

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    Overall and based on this FET device selection vs tested failure mode doc:
    http://www.infineon.com/dgdl/apec11mosfet.pdf?fileId=5546d462533600a40153574008aa3ec2

    It seems the Trench IRFP3206 is a reasonable selection because:
    1) Slower switching is employed with high forward currents (low RdsOn)
    2) 60 Vds devices exhibit similar ruggedness for avalanche and Fwd Bias SOA with both Planar & Trench type FET tech. At 100V Planar is better.
    3) Superior reverse recovery characteristics to Planar tech.

    On a related matter, in selecting a replacement for the 50SQ080 Schottky flywheel, now out of production, I have found this to be useful:
    http://www.st.com/content/ccc/resou...df/jcr:content/translations/en.DM00098381.pdf

    I am selecting a VS-20CTQ150 to deliver about 2KA pulse capability total across both legs and for simple heatsinking. On sale for $0.65 at Newark.com.
    http://www.farnell.com/datasheets/2243697.pdf?_ga=1.147375742.870694276.1485566007

    Regarding using a G4 bayonet lamp for the charge dissipation in the Lo ESR capacitor 'snubber' :This is done as a power resistor ($5+) is very expensive for the application vs around $0.15 per lamp. I'll use a pair of 10W G4 lamps in parallel (with the capacitor) to provide some longevity redundancy should one fail. They function a bit like high wattage PTCs.
     
    Last edited: Mar 30, 2017
  7. shortbus=

    shortbus= Well-Known Member

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    The original post in this tread is what lead me to make my post. Trying to get multiple mosfets to play well together seems to be an ongoing problem on many forums. That's why my suggestion of a single large mosfet.

    Another route would be IGBT's they use the same gate drivers as mosfets.
     
  8. Mosaic

    Mosaic Well-Known Member

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    Your post is appreciated. I did look at a power FET early on, but cost is a bit prohibitive. In terms of manufacturing a cheaper FEtused 4 times gets to pricebreaks4 x faster than large units once longevity can be established .
     
  9. Mosaic

    Mosaic Well-Known Member

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    To summarize this thread and make it easier for folks to take away useful info:

    1) It turns out that FET matching seems not to be the causative factor in random failure.
    2) The devices were exceeding the max SOA avalanche currents even though their temperature was managed, thus making for failure at some point.:arghh:
    3) A flywheel solution was designed & tested which is capable of tolerating the >800A of peak flywheel currents and reverse load (battery) polarity.:D
    4) Energy output of the Back EMF caused by parasitic inductance was quantified using capacitive storage capture of the energy which can be used to quantify the parasitic inductance.
    5) A secondary effect of hi current switching transients hitting the FET gate via parasitic Cgd was looked at and no real benefit was found by attempting RC snubbing. Probably due to the fact that Cgd is over 1000pF on the IRFP3206. Reducing Gate Drive impedance helps somewhat, but gate transients may not be the problem here.
    6) Thermal improvement (reduction) delta of 5X was achieved on the FET bank after snubbing the avalanche as indicated by FLIR camera monitoring.
    7) Long term stability cannot be assessed at this time, but the SOA is now obtained on all parameters as the FETs have active thermistor feedback for current limiting.

    Have a look at Table 2 in this doc for the parameters that matter when paralleling MOSFETs based on parameter importance:
    http://www.infineon.com/dgdl/para.pdf?fileId=5546d462533600a401535744b4583f79

    Thanks to all those who made suggestions. I feel much more confident going forward.:)
     
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  10. alec_t

    alec_t Well-Known Member Most Helpful Member

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    A useful smmary. Thanks for that.
     
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  11. Mosaic

    Mosaic Well-Known Member

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    One more thing: while evaluating the Gate failure I realized that a simple way to evaluate a 'shorted' NFET in a bank is to check the Rgd. In my case the in circuit Rgd is 1.9MΩ normally. The blown NFET Rgd is 38Ω, as a result with 5Ω gate resistors the GOOD NFETS Rgd all look like 10Ω> Blown NFET Rgd or 48Ω. Removing the shorted NFET returns measurements to normal.
     
  12. Mosaic

    Mosaic Well-Known Member

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    By using an incandescent lamp to burn off the backemf power ( I have seen up to 20W of backemf), I realised I needed a fail-safe when the lamp goes south as it must one day. As it happens once the lamp is burnt out the Lo ESR , parallel 2K uf 50V cap voltage starts to ramp up, being charged by the backemf pulses. In a short time it exceeds 30V. I added an 18V zener feeding a 5V SMD relay to crowbar the main fuse. Thus once the capacitor's voltage exceeds 23V the failsafe executes.
     
  13. ronsimpson

    ronsimpson Well-Known Member Most Helpful Member

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    upload_2017-5-23_7-41-37.png
    It is this "package". The plate that bolts to heatsink is isolated. (not connected to the MOSFET) Most heat sink pins are connected to the Drain. In this case the heatsink is insulated up to 2500 volts.
     

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