Sanjay Sarker
New Member
Hi. I am facing problem to generate non overlapping signal from multiple overlapping digital signal. If any one have any idea or circuit design please share.
Actually We taken 9 bits out put from SAR lower block where we used DFF including comparator decision and upper block used DFF for shift register. We could make upper block,s out put non overlapping by using non overlapping clock. But final output with comparator decision could not make non overlapping.
Actually We taken 9 bits out put from SAR lower block where we used DFF including comparator decision and upper block used DFF for shift register. We could make upper block,s out put non overlapping by using non overlapping clock. But final output with comparator decision could not make non overlapping.
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