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How to design a 4-bit ripple down counter using four T flip-flops?

Discussion in 'Homework Help' started by morgan329, Jul 7, 2010.

  1. morgan329

    morgan329 New Member

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    How to design a 4-bit ripple down counter using four T flip-flops and no other components? Could anyone give me some suggestion? Thank you.
     
  2. crutschow

    crutschow Well-Known Member Most Helpful Member

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  3. morgan329

    morgan329 New Member

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    Yes, but I do not understand what a 4-bit ripple DOWN counter is?
     
  4. dave

    Dave New Member

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  5. Mikebits

    Mikebits Well-Known Member

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    Well it is like this. Each clock pulse ripples from one FF to the next (See above link). To count up the chain goes from 0000--->1111 and to count down you go from 1111--->0000.
     
  6. SLACer

    SLACer New Member

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    T flip flop basics

    The T flip-flop is basically a modified D flip-flop. It has a gated feedback loop from the Q outputs to the internal D input. The gate control is the T input pin.

    When a logic zero is applied to the T pin The Q output is fed back to the internal D input.
    When a logic one is applied to the T pin The NOT-Q output is fed back to the internal D input.

    so think in terms of the D flip-flop operation. When the NOT-Q is fed back to the D The output Q will divide the clock by two. This is the condition required to build an asynchronous, or cascade counter.

    FOR A DOWN COUNT
    Connect all of the clear and set pins to logic one.
    Connect; the T input pins to a logic one.
    Connect; the first stage clock input to the clock source.
    Connect; the Q of the first stage to the clock input in the next stage.
    Repeat this step until all of the flip-flops are connected.

    FOR AN UP COUNT
    Connect all of the clear and set pins to logic one.
    Connect the T input pins to a logic one.
    Connect the first stage clock input to the clock source.
    Connect the NOT-Q of the first stage to the clock input in the next stage.
    Repeat this step until all of the flip-flops are connected.

    Read the output data from the Q outputs of the flip-flops.

    The flip-flop connected to the clock is the "two to the zero bit" the next one is the "two to the one bit" each one after that is assigned the next base two value till they are all assigned. The output is read in strait binary which easily converts to decimal numbers.
    You can make a cascade counter with as many bits as you please.

    Beware of the accumulated time delays of that type of circuit. When the accumulated time delays for that type of circuit exceed the clock pulse it will become unreliable. A good rule of thumb is that the time delay should not exceed between half and two thirds of the shortest clock pulse.
     
    Last edited: Jul 21, 2010

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