How does the AVR do one clock per instruction?

[blueroomelectronics]

I'm curious how does AVR acheive a one clock per instruction speed?
Is it a larger pipeline prefetch?
Execution on both clock edges?

 

[HarveyH42]

Here are a couple of pages from the ATTiny13 datasheet. Might give you some insight. Never really bothered with trying to understand it myself.

 

[Leftyretro]

I'm curious how does AVR acheive a one clock per instruction speed?
Is it a larger pipeline prefetch?
Execution on both clock edges?

It mostly means there is a ton of parallel paths between all the buses/registers/memories (data and program) and the central ALU device.

Upon decoding of the instructions there are enables placed on all elements needed to perform the specific instruction with just a single clock pulse, and yes I would assume that both the leading and trailing edges are needed to make that all happen in one cycle.

It's a classic tradeoff of how much logic to expense Vs speed of operation. Also in retrospect, IF a 4 cycle per instruction processor can be clocked 4X the clock speed of a single clock per instruction processor, does the user of the device really care?


Lefty

 

[eblc1388]

Also in retrospect, IF a 4 cycle per instruction processor can be clocked 4X the clock speed of a single clock per instruction processor, does the user of the device really care?
Lefty

Power consumption at 4X clock speed? RF Emission level? So I would rephrase:

If a 4 cycle per instruction processor can be clocked at 4X the clock speed of a single clock per instruction processor while consuming no increase in overall power, does the user of the device really care?

 

[Leftyretro]

Power consumption at 4X clock speed? RF Emission level? So I would rephrase:

If a 4 cycle per instruction processor can be clocked at 4X the clock speed of a single clock per instruction processor while consuming no increase in overall power, does the user of the device really care?

Good point. Microprocessor design like most any complex design is a series of (many, often conflicting) trade-off decisions. Like if a hardware multiply/divide function should be included or if just micro-coded shift instructions be used to accomplish the same task.

I recall one in-house mini-computer design I worked on in the 70s that only had one real hardware register, the ALU accumulator, the others (program counter, variable registers, etc) were just reserved addresses in the main core memory, less logic required, slower speed but fast enough to do the purpose task of the in house application.

Logic design of computers is a fascinating subject. Even a product series like the famous DEC PDP-11 series of the 70s & 80s had tremendous differences in implementing the many models all with the standard PDP-11 instruction set.

Lefty

 

[eblc1388]

Yes. Respect!

And without the hard work of so many people involved in earlier pioneering work in computing, we would not have what we have today.