1. Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.
    Dismiss Notice

Help with non-overlapping clock generator

Discussion in 'Homework Help' started by andrea22, Oct 12, 2010.

  1. Roff

    Roff Well-Known Member

    Joined:
    May 16, 2003
    Messages:
    7,757
    Likes:
    89
    Location:
    Idaho, USA
    I'm out of ideas.
     
  2. ericgibbs

    ericgibbs Well-Known Member Most Helpful Member

    Joined:
    Jan 4, 2007
    Messages:
    21,176
    Likes:
    644
    Location:
    Ex Yorks' Hants UK
    ONLINE
    hi Ron,
    I have been following with interest this thread, I applaud your persistence.:)

    I think what the OP is doing is he is adding the propagation delay at the start and at the end of the square wave pulses, so he always finishes up with an overlapping clock pulse train.

    IMO he should consider the propagation delay as acting on the leading and trailing edges [ high to low and low to high transition] at the gate inputs.

    example:
    Say the propagation delay is 10uSec thru the gate for the leading edge, the leading edge will change the state of the gate output 10uS later, so the pulse width has 'shrunk' in width by 10uS.
    The same applies to the trailing or falling edge, it takes 10uS to propagate thru the gate, so the pulse width has 'shrunk' by a further 10uS.
    As this happens thru every gate the pulse width will get shorter and at the outputs the two pulse streams will not overlap..

    Regards.
     
  3. Roff

    Roff Well-Known Member

    Joined:
    May 16, 2003
    Messages:
    7,757
    Likes:
    89
    Location:
    Idaho, USA
    Eric, if leading and falling edges have the same delay (through an inverter, or whatever), the entire pulse will be delayed by that amount, but the pulse width will not change.
    The key to that circuit is the S-R flip-flop with delays added in the feedback legs.
     
    Last edited: Oct 14, 2010
  4. dave

    Dave New Member

    Joined:
    Jan 12, 1997
    Messages:
    -
    Likes:
    0


     
  5. ericgibbs

    ericgibbs Well-Known Member Most Helpful Member

    Joined:
    Jan 4, 2007
    Messages:
    21,176
    Likes:
    644
    Location:
    Ex Yorks' Hants UK
    ONLINE

    hi Ron,
    IMO the response time of the gate should be a better way to explain the shortening on the pulse width rather than the gate delay.

    Its been my observation that when the pulse edge response time of a gate increases the pulse width is reduced.

    I cannot understand why the OP is having problems, when following your description, how he gets an over lapping clock.???
     
  6. Roff

    Roff Well-Known Member

    Joined:
    May 16, 2003
    Messages:
    7,757
    Likes:
    89
    Location:
    Idaho, USA
    Even if the gates and inverters had zero rise and fall times, but finite delay, the circuit would still create nonoverlapping clocks.
     
  7. andrea22

    andrea22 New Member

    Joined:
    Oct 12, 2010
    Messages:
    24
    Likes:
    0
    Ron,
    Rise time and fall time are actually delay time.
    You know that delay time is usually: tdelay=1/2*(t_rise+t_fall).
    This equation is for CMOS inverter anad every logic circuit realised in CMOS technology can be equivalent
    with CMOS inverter.
    I draw timing diagrams on my way.
    Anyway,thanks for your help.

    Andrea
     
    Last edited: Oct 17, 2010
  8. Roff

    Roff Well-Known Member

    Joined:
    May 16, 2003
    Messages:
    7,757
    Likes:
    89
    Location:
    Idaho, USA
    Who told you that? Can you provide a link?
    Propagation delays are separate from output transition times, and may or may not match the equation you posted. It all depends on the internal circuitry and the complexity of the gate.
     
  9. crutschow

    crutschow Well-Known Member Most Helpful Member

    Joined:
    Mar 14, 2008
    Messages:
    10,592
    Likes:
    477
    Location:
    L.A., USA Zulu -8
    I agree with Ron. Rise and fall times may contribute to delay, but a circuit can certainly have a much larger delay time then the rise and fall times, it depends largely upon the amount of circuitry been the input and output. Look at the difference been an inverter delay and a flip-flop delay, for example.
     
  10. andrea22

    andrea22 New Member

    Joined:
    Oct 12, 2010
    Messages:
    24
    Likes:
    0
    tpdr : rising propagation delay
    – From input to rising output
    crossing VDD/2
    tpdf: falling propagation delay
    – From input to falling output
    crossing VDD/2
    tpd: average propagation delay
    – tpd = (tpdr + tpdf)/2
    tr: rise time
    – From output crossing 0.1 VDD to 0.9 VDD
    tf: fall time
    – From output crossing 0.9 VDD to 0.1 VDD
    tpdr=1/2*tr
    tpdf=1/2*tf
     

    Attached Files:

    Last edited: Oct 17, 2010
  11. Roff

    Roff Well-Known Member

    Joined:
    May 16, 2003
    Messages:
    7,757
    Likes:
    89
    Location:
    Idaho, USA
    Simple CMOS logic gates and inverters can approach the performance of your diagrams. More complex gates, like 8-input gates, e.g. CD4068, exclusive ORs, etc. have internal circuitry that contributes to delay. Even NANDs and NORs have internal buffering that contribute to delay.
    TTL gates have delay that is due to storage time, which is totally independent of transition times.
    Your drawing is much too simplistic.
     
  12. andrea22

    andrea22 New Member

    Joined:
    Oct 12, 2010
    Messages:
    24
    Likes:
    0
    I tell you that I don't know type number of cmos logic gates,
    and I don't need that.
    I 've done simulation in ORCAD PSpice.
    I draw CMOS inverter with 1 p-channel MOSFET and 1 n-channel MOSFET.
    CMOS nand gate is consist of two serial n-channel MOSFETs,and two parallel p-chanell MOSFETs.
     

    Attached Files:

    Last edited: Oct 18, 2010
  13. crutschow

    crutschow Well-Known Member Most Helpful Member

    Joined:
    Mar 14, 2008
    Messages:
    10,592
    Likes:
    477
    Location:
    L.A., USA Zulu -8
    Certainly a simple two transistor inverter has very little delay time as compared to the rise and fall times. But delay times can be much larger than rise and fall times in complex circuits. They are not the same parameter.
     
  14. andrea22

    andrea22 New Member

    Joined:
    Oct 12, 2010
    Messages:
    24
    Likes:
    0
    I don't need complex circuit.
    I told you that my circuit is quite simple.
    Thanks for help.
     
  15. Roff

    Roff Well-Known Member

    Joined:
    May 16, 2003
    Messages:
    7,757
    Likes:
    89
    Location:
    Idaho, USA
    If you were implementing this circuit within an IC, your gate schematics are exactly what I would use.
     
  16. andrea22

    andrea22 New Member

    Joined:
    Oct 12, 2010
    Messages:
    24
    Likes:
    0
    Do yo know why in dynamic shift register non-overlapping clocks are used?
    Or why this circuit doesn't work with overlapped clocks?
     

    Attached Files:

  17. Roff

    Roff Well-Known Member

    Joined:
    May 16, 2003
    Messages:
    7,757
    Likes:
    89
    Location:
    Idaho, USA
    There are parasitic capacitors at the gate inputs that act as hold capacitors. Each clock samples the output of the previous gate. If the clocks overlapped, data could shoot through all the inverters during the overlap time, or at least degrade the logic levels held on the capacitors to the point where errors would occur.
     
  18. andrea22

    andrea22 New Member

    Joined:
    Oct 12, 2010
    Messages:
    24
    Likes:
    0
    Do you have any literature about pass transistors?
    These are my diagrams.The third diagrams is at the output of pass transiastor.
    Why is happening when Phi1=0,Vin=Vdd and Phi1=0 and Vin=0?
     

    Attached Files:

    Last edited: Oct 20, 2010
  19. Roff

    Roff Well-Known Member

    Joined:
    May 16, 2003
    Messages:
    7,757
    Likes:
    89
    Location:
    Idaho, USA
    That is the result of the clock coupling through the parasitic capacitance of the pass transistor, transferring a little charge to the hold capacitor. It's a capacitive voltage divider.
     
  20. andrea22

    andrea22 New Member

    Joined:
    Oct 12, 2010
    Messages:
    24
    Likes:
    0
    These are diagrams for voltage in points:A0,A1,A2,A3.
    This is ok?
     

    Attached Files:

  21. Roff

    Roff Well-Known Member

    Joined:
    May 16, 2003
    Messages:
    7,757
    Likes:
    89
    Location:
    Idaho, USA
    If the inverters are powered with 3 volts, they look good.
     

Share This Page