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Digital Frequency Control

Discussion in 'Electronic Theory' started by Space Varmint, Jul 22, 2008.

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  1. Space Varmint

    Space Varmint New Member

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    RadioRon & I were discussing digital frequencies control solutions in another thread about radio transmission & reception and kind of decided that the topic deserved it's own category. So I figured I would start here and post an old single loop PLL circuit. In here we hope to get input from anyone who has a good suggestions or just some research you have come across. Anything about digital frequency controls. Pros & cons of various techniques. Recent breakthroughs. Even old theory and descriptions for the newbies.

    The circuit below though it is a working PLL (Phase Lock Loop) digital frequency synthesizer, it is being used to describe the basic components of PLL. Q1 is configured into a Hartley oscillator. This is where the output from the frequency synthesizer is produced and fed to the radio circuits as the oscillator. In this circuit the oscillator is running at 400 MHz. Because the oscillator is running at such a high frequency, it is necessary to divide the frequency down to something that is workable for the TTL to used later. This is the job of U2 which is a prescaler. A prescaler is nothing more then a counter being used as a frequency divider except for one thing. It is composed of ECL (Emitter Coupled Logic) which is transistors configured in common-collector or emitter-follower arrangement. The reason for this is, transistors switch much faster in this type of arrangement. Overall it it just a divide by 10 counter.

    So now the output of the prescaler is 40 MHz is being fed to a much cheaper TTL counter which is being used as a divide by 16 divider. This leaves us with an output of 2.5 MHz. This is fed to the comparator. This is a rather old type of frequency comparator. Now days IC's are available that use a combination of XOR gates and flip-flops that can do more than just detect phase shifts but also can detect frequency to the point that a PLL can lock up on a harmonic frequency of say, times 2 but the steering logic in more modern phase detectors/comparators will prevent this phenomena.

    Now we need a stable reference frequency and as we all know a crystal can be quite stable, so we build a crystal oscillator. IC1a & IC1b make a good cheap & dirty square-wave oscillator and we can use gate IC1c as a 180 degrees phase shift for the comparator. You may use a sign-wave oscillator as well here.

    So we feed the divided down oscillator signal and the reference oscillator signal to the comparator or phase detector and both are at the same frequency only one of the signals is crystal locked. In most of your phase detectors you usually only need these two signals, but this type here requires a 180 degrees phase shifted signal as well. It is an old comparator circuit and is a rare bird these days. Often times you can use just these two signals going to an XOR gate and will work the same.

    The output of the phase detector will be a chopped up AC signal of the two original signals (divided down oscillator/VCO & reference osc). The average voltage of the AC signal will shift up and down very quickly as the VCO (oscillator) frequency drifts higher or lower then the reference frequency times the division factor. Visualize them running at same frequency for all practical purposes. This being the primary voltage of interest, also known as "error DC", we can amplify this signal with a DC amplifier. A DC amplifier is an amplifier with no coupling or bypass capacitors. We do not want to block the DC.

    Being that this is still an AC signal, we do not want to apply it to the VCO yet or it will cause the VCO to jump all over the place. We are only interested in the overall average voltage of "error DC". R7 & C8 compose a simple "loop fiter" to smooth out the AC and create an average DC.

    No we see that the output of the loop filter is applied to the varactor diode of the main oscillator. The varactor being in the tank circuit of the oscillator makes it a VCO (Voltage Controlled Oscillator) since the varactor will change it's spacing across the juction of the diode, effectively changing it's capacitance. Now we have a way for the feedback loop to self adjust any drift that may occur by comparing to the locked signal from the crystal reference frequency.

    This is a description of the basic lock loop. The frequency can be changed in a number of ways. In the case of this circuit, one method might be to jam load the counter U1 with a divide by 15 count instead of divide by 16. This will cause the frequency to jump down 2.5 MHz. The step rate is determined by the reference frequency where it is applied to the phase detector. Had we divided both signals down by an additional divide by 10 and then apply the signals to the phase detector, the step rate would be 250 KHz.

    So these are the basic building blocks of a PLL digital frequency synthesizer. Then there is another commonly use technique referred to as DDS (Direct Digital Synthesis) where the actual oscillator frequency is built by digital D to A converters.

    Any input is welcome. The object will be some of the most efficient superior techniques known today but we do not want to leave out any of the history of signal processing.
     

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    Last edited: Jul 22, 2008
  2. RadioRon

    RadioRon Well-Known Member

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    Important improvements over the basic PLL described by SV include Dual Modulus Prescaling, sometimes called pulse swallow counting, and Fractional-N counting.

    Dual modulus has been around for a long time, while Fractional-N is more recent. Both techniques bring greater flexibility to the counter used to feed back the VCO signal to the phase detector, and are especially useful at VHF and higher frequencies where high speed prescalers are essential. These methods allow the designer to create much finer resolution frequency steps without necessarily using very high counter ratios or very low phase comparison frequencies.

    Here is more details:
    on dual modulus prescaling, refer to section 4.3 of this datasheet:
    http://www.electro-tech-online.com/custompdfs/2008/07/MC145151-2.pdf

    On Fractional-N synthesis:
    http://www.electro-tech-online.com/custompdfs/2008/07/1100Appel34.pdf

    Many synthesizer IC data sheets also provide basic information about these configurations as well so they make for good reading.
     
    Last edited: Jul 22, 2008
  3. Space Varmint

    Space Varmint New Member

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    Hey thanks RR!

    Yeah, dual modulus gives a little extra flexibility. I have not experienced the fractional N. I will have to look that up. I hope we get more input in this thread. This is a very important topic I would think. I suppose I'm kind of shooting for a good brain storm session here but maybe it's not very interesting to some. I did notice when I joined this sight that there were allot of very intelligent people here. A little too much bickering mixed with sarcasm and getting off topic which doesn't need to be. But all & all I think there are some really sharp cookies around these here parts. I had learned a long time ago, there is no such thing as a stupid question. Ideas. Ideas are what is needed here. Tell them Ron. Tell them how cumbersome dual and mult-loop synthesizers are. What is the key to a good radio? Noise! Noise is the killer. When you go into multi-loops you are having to deal with more and more noise. As far as I know DDS & PLL are the only two digital methods. OK, lets discuss the two. Maybe we can get some interest here.

    PLL:

    A single loop PLL is discussed above. The problem with PLL is in my opinion, the major draw back, the resolution. A 10 KHz resolution is really about the best you can get and keep the signal clean at the same time in single loop. What that means is, if I am transmitting or receiving at a frequency of 100 MHz and I what to go to the next frequency, I will push a button UP or Down. If I go up it will go to 100.010 MHz. 5 KHz can give satisfactory results but what is the standards for what is considered cleanliness? The FCC has a few specs that apply directly to a good PLL. One is known as "Full Quiet" which is 60 db down. WHat is 60 db down from what you ask? If we look at the single loop PLL above, it was discussed how resolution is obtained. It was stated that the reference frequency was the determining factor. Where the VCO output and the crystal reference oscillator are divided down and compared together in the phase detector. The divide ration of the reference at that point determines the resolution. The loop filter smooths out the AC fluctuations, but to a point. The energy still exists. What will be the result in what are known as phase sidebands. So you will have a center frequency of say 100 MHz being generated from the VCO but you will also a frequency being generated of 100.010 MHz with 10 KHz resolution and you will have a frequency of 99.990 MHz. So both sides of center frequency you have these sidebands generated either side of center frequency. Another level of sidebands exists another 10 KHz either side or 100.020 & 99.980. They will be even lower in energy than the first two sidebands. And this pattern continues until there is no more power to generate. The first two sidebands are the major ones that need to be dealt with. So when the FCC refers to "Full Quite" (60db down) they are discussing the first two sidebands...100.010 & 99.990. Again the loop filter is what determines their energy level or how many DB down the sidebands will be. The more you reduce the sidebands the less bandwidth you will have with your PLL. So you may have a PLL that sounds awesome with 120 DB down on the phase sideband but may only have a bandwidth of 100 KHz. That means you will be be able to move up or down 50 KHz from center frequency or 10 total frequency steps when you push the button to change frequency. We will go into daul loops later and why they are used and more importantly the drawbacks.

    DDS:

    DDS (Direct Digital Synthesis) uses no oscillator. It is a signal that is built using D2A converters. It can be as simple as a counter being made to count and the output goes through D2A. This of course is completely unnatural and the odd components that are derived from this synthetically built signal are referred to as aliasing. They are being used but you have to consider what they are being used for. If they are being used in the cell phone industry (no offense Ron) then you have seen thows eye sore cell towers everywhere. They are repeater stations which pick up the signal an amplify it and re-transmit it over and over again. In this case, since receiver quality is largely a function of signal-to-noise, we have plenty of signal to deal with and the noise is less of a factor.
     
    Last edited: Jul 23, 2008
  4. dave

    Dave New Member

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  5. mneary

    mneary New Member

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    All DDS systems I've seen or designed have an oscillator. Examples, please.
     
  6. saturn1bguy

    saturn1bguy New Member

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    I'm not sure if this is what you're looking for, but I recall a digital sinewave generator from years ago. I'm hazy now on the details, but it sported output resolution of a single Hz, as I recall, and was meant for use as a bench instrument. It used pretty standard counters, including keypad and display, but counted out a single "digitized" sinewave stored in EPROM, over and over, ad infinitum. Somehow the ARRL handbook from 1987 comes to mind, I think.

    If I recall more, I'll post again, or, if none of this applies here, well then never mind :)
     
  7. Space Varmint

    Space Varmint New Member

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    Your talking about the clock for the counter. Yes, I believe it is Nyquist theorem that states the clock must be at least 3 times the generated frequency to be practical. But the frequency is built digitally.
     
  8. Space Varmint

    Space Varmint New Member

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    Oh cool! Like 1 Hz? yeah I'd like to see that. Of course it would be nice if it were simple and low power. I did use an HP 8662 that had that kind of resolution. It was a big old thing and at the time cost 80,000 dollars. A little much to out in a radio.
     
  9. mneary

    mneary New Member

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    Please describe a purely digital frequency source. Without an oscillator/crystal.
     
  10. saturn1bguy

    saturn1bguy New Member

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    This project wasn't too bad, not too complex. I've contacted the person who has the real information. If I get anything back, I'll pass it on. But, yes, I do recall 1Hz precision. That's what grabbed my attention back then.

    EDIT: After doing some cursory research on DDS, it appears that the unit in question definitely uses DDS principles, as it employed both a phase accumulator and sine lookup table (in EPROM). So, this particular project is likely quite antiquated compared to more modern methods...
     
    Last edited: Jul 24, 2008
  11. Space Varmint

    Space Varmint New Member

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    Oh NO! Let's see it. There is no such thing as antiquated. Not in my book. Good is good. Could be something that slipped by. Let me put it this way. One reason I am so delighted to get an ARRL Handbook is that I am fascinated with the stuff people have come up with all the time. Take for instance the first single sideband transmitters & receivers. These guys actually built this phase shifting network out of diodes where they used it to cutoff the carrier and one sideband. Utterly amazing!
     
  12. Space Varmint

    Space Varmint New Member

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    OK guy. I'm not wanting to fight with you. I'm just trying to get a big conglomeration of frequency control stuff going here. Technically your right & I'm right because there is a clock being used to operate the counters. I suppose you could call it a conversion circuit in a technical sense, but the signal f0 is being built digitally. It is not an oscillator that is controlled or manipulated.
     
  13. saturn1bguy

    saturn1bguy New Member

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    Right. I'll follow up if/when I get something back from my buddy...
     
  14. Space Varmint

    Space Varmint New Member

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    Please do. Not getting allot of variation here. Maybe it's just me but I find this topic invaluable. I like your signature. Wouldn't it be funny if that were true. I know I would be turning screw drivers all day and selling product.

    I've been trying to find a good dual loop block diagram but not having much luck. I was gonna go ahead and start describing dual & multiple loop.
     
  15. Space Varmint

    Space Varmint New Member

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    Well basically the reason for dual loops is to take advantage of the characteristics of a high or fine resolution loop & a low resolution loop and to combine them though mixers which add more junk and mix the phase sidebands as well. Not you have a fancy filtering job on your hands not to mention bandpass considerations etc.

    What are the characteristics you might ask? ;)

    1. A fine resolution loop need more filtering. This is done in the loop filter. The more filtering required will lower the bandwidth of the loop.

    2. Conversely a low or broad resolution loop does not need as much filtering and therefore will have a much wider band width.

    Often what is done is to use multiple VCO's combined with two or more loops. There are ways of getting around the fine resolution problem. I have had some success by using a processor to generate the reference frequency which will be produced off an internal timer. Then you can jam load the counter with different values. It is difficult to predetermine the results which would greatly reduce the time needed to build your lookup tables.

    Anyway, I have pretty spilled my guts. I was hoping some of you geniuses would have some research or techniques or theories worth looking into. Maybe I'm barking up the wrong tree. Everybody wants free power now days, but I will tell you, communications will be very important. If something happens to one or two of those satellites drifting around in space, you will be surprised at the dependency we have developed on these things. It bothers me. I don't know about you?
     
  16. Space Varmint

    Space Varmint New Member

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    Pitfall warning!!!!

    Do not use Armstrong oscillators as your VCO. No range! I'm going back to Hartley.
     
  17. kchriste

    kchriste New Member Forum Supporter

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    Last edited: Aug 18, 2008
  18. Space Varmint

    Space Varmint New Member

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    Thanks Kchiste. I guess I should have mentioned I'm looking for something in the HF range. By the time you divide down 250 MHz to say 10 MHz, that divide ratio becomes the HF bandwidth. Another thing. I don't want a divided signal is my f0 signal. Too much harmonic content. Spectral purity is key in a good HF receiver.
     
  19. Nigel Goodwin

    Nigel Goodwin Super Moderator Most Helpful Member

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    You don't divide down, you hetrodyne down, so you get the full bandwidth. This is how continuously tuned HF receivers work.
     
  20. Space Varmint

    Space Varmint New Member

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    Good point! Yes I know you can do this. It scares me to have so many unwanted components on the 1st LO. I may try the multiple VCO approach. I just built the Hartley and it is very spectrally pure. Beautiful sinusoidal sine-wave! You seem to know your stuff Nigel. Have you built any receivers?

    Still, when you mix it down to produce a first LO then divide that down for your reference. If you want say 10KHz step rate (for instance) then when you hop to the next step it will be multiplied through the mixer still limiting your range.

    Wait a minute. Have to think that through. I got so much crap to do right now. Just ain't got time to think about it...lol

    I'll be mad if I have to do this oscillator again. Especially after fighting with the Armstrong.
     
    Last edited: Aug 19, 2008
  21. Nigel Goodwin

    Nigel Goodwin Super Moderator Most Helpful Member

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    Not for years, and only simple ones.

    I would suggest you buy the ARRL or RSGB manuals, these are essential for anything radio based - everyone here should really have one or the other (or both).
     
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