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decoder for 8051

Discussion in '8051/8951' started by Parth86, Oct 22, 2014.

  1. Parth86

    Parth86 Member

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    hello
    4 bits can decode 16 things.

    5 bits can decode to 32 things,

    6 bits can decode 64 things.
    etc, etc..
    8 bit can decode 256 things
    16 bit can decode 512 things
    can anyone tell me which decoder is used for 8051 microcontroller ?
     
    Last edited by a moderator: Oct 22, 2014
  2. Pommie

    Pommie Well-Known Member Most Helpful Member

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    Your question doesn't make any sense.

    BTW, 16 bits can represent 65536 states - not 512.

    Mike.
     
  3. ronsimpson

    ronsimpson Well-Known Member Most Helpful Member

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  4. dave

    Dave New Member

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  5. ronsimpson

    ronsimpson Well-Known Member Most Helpful Member

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    upload_2014-10-22_22-17-28.png
     
    • Like Like x 1
  6. Parth86

    Parth86 Member

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    ok I want to make table as you shown in your post
    actually I want to make table for following example

    16 bits can represent 65536 states
    ram_rd_sel
    ram_wr_sel
    src_sel1
    src_sel2
    alu_op
    wr = 1'b0;
    psw_set
    cy_sel
    pc_wr
    pc_sel
    imm_sel
    src_sel3
    comp_sel
    bit_addr ;
    rom_addr_sel = OC8051_RAS_DES;
    ext_addr_sel = OC8051_EAS_DC;

    when all input are 0 then do NOP operation

    Code (text):

    module decoder (clk, rst, op_in, ram_rd_sel, ram_wr_sel, bit_addr, wr, src_sel1, src_sel2, src_sel3, alu_op, psw_set, cy_sel, imm_sel, pc_wr, pc_sel,
                    comp_sel, eq, rom_addr_sel, ext_addr_sel, wad2, rd, write_x, reti,
       

    );
    input clk, rst, eq;
    input [7:0] op_in;
    output wr, reti, write_x, bit_addr, src_sel3, rom_addr_sel, ext_addr_sel, pc_wr, wad2;
    output [1:0] ram_rd_sel, src_sel1, src_sel2, psw_set, imm_sel, cy_sel, pc_sel;
    output [2:0] ram_wr_sel, comp_sel;
    output [3:0] alu_op;
    output rd;
    reg reti, write_x;
    reg wr,  bit_addr, src_sel3, rom_addr_sel, ext_addr_sel, pc_wr, wad2;
    reg [1:0] psw_set, ram_rd_sel, src_sel1, src_sel2, imm_sel, pc_sel, cy_sel;
    reg [3:0] alu_op;
    reg [2:0] comp_sel, ram_wr_sel;
    reg [1:0] state;
    reg [7:0] op;
    always @(rst or op_in or eq or state or op)
    begin
      if (rst) begin
      ram_rd_sel = OC8051_RRS_DC;
      ram_wr_sel = OC8051_RWS_DC;
      src_sel1 = OC8051_AS1_DC;
      src_sel2 = OC8051_AS2_DC;
      alu_op = OC8051_ALU_NOP;
      imm_sel = OC8051_IDS_DC;
      wr = 1'b0;
      psw_set = OC8051_PS_NOT;
      cy_sel = OC8051_CY_0;
      pc_wr = OC8051_PCW_N;
      pc_sel = OC8051_PIS_DC;
      comp_sel = OC8051_CSS_DC;
      bit_addr = 1'b0;
      src_sel3 = OC8051_AS3_DC;
      rom_addr_sel = OC8051_RAS_PC;
      ext_addr_sel = OC8051_EAS_DC;
      wad2 = OC8051_WAD_N;
        case (state)
          2'b01: begin
        casex (op)
          OC8051_ACALL :begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_SP;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = 2'bxx;
              alu_op = OC8051_ALU_NOP;
              imm_sel = OC8051_IDS_PCH;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              comp_sel = OC8051_CSS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_AJMP : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = 2'bxx;
              alu_op = OC8051_ALU_NOP;
              imm_sel = OC8051_IDS_DC;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              comp_sel = OC8051_CSS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_LCALL :begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_SP;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = 2'bxx;
              alu_op = OC8051_ALU_NOP;
              imm_sel = OC8051_IDS_PCH;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              comp_sel = OC8051_CSS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          default begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
          end
        endcase
        end
        2'b10:
        casex (op)
          OC8051_CJNE_R : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = !eq;
              pc_sel = OC8051_PIS_ALU;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DES;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_CJNE_I : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = !eq;
              pc_sel = OC8051_PIS_ALU;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DES;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_CJNE_D : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op =OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = !eq;
              pc_sel = OC8051_PIS_ALU;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DES;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_CJNE_C : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = !eq;
              pc_sel = OC8051_PIS_ALU;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DES;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_DJNZ_R : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = eq;
              pc_sel = OC8051_PIS_ALU;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DES;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_DJNZ_D : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = eq;
              pc_sel = OC8051_PIS_ALU;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DES;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_JB : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = eq;
              pc_sel = OC8051_PIS_ALU;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_BIT;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_JBC : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_D;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = eq;
              pc_sel = OC8051_PIS_ALU;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_BIT;
              bit_addr = 1'b1;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_JC : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = eq;
              pc_sel = OC8051_PIS_ALU;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_CY;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_JMP : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_Y;
              pc_sel = OC8051_PIS_ALU;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_BIT;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_JNB : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = !eq;
              pc_sel = OC8051_PIS_ALU;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_BIT;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_JNC : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = !eq;
              pc_sel = OC8051_PIS_ALU;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_CY;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_JNZ : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = !eq;
              pc_sel = OC8051_PIS_ALU;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_AZ;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_JZ : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = eq;
              pc_sel = OC8051_PIS_ALU;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_AZ;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOVC_DP :begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = 2'bxx;
              src_sel3 = OC8051_AS3_DP;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_Y;
              rom_addr_sel = OC8051_RAS_DES;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOVC_PC :begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = 2'bxx;
              src_sel3 = OC8051_AS3_DP;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_Y;
              rom_addr_sel = OC8051_RAS_DES;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_SJMP : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_Y;
              pc_sel = OC8051_PIS_ALU;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          default begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
          end
        endcase
        2'b11:
        casex (op)
          OC8051_CJNE_R : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_OP2;
              alu_op = OC8051_ALU_PCS;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP3;
              src_sel3 = OC8051_AS3_PC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_CJNE_I : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_OP2;
              alu_op = OC8051_ALU_PCS;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP3;
              src_sel3 = OC8051_AS3_PC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_CJNE_D : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_OP2;
              alu_op = OC8051_ALU_PCS;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP3;
              src_sel3 = OC8051_AS3_PC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_CJNE_C : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_OP2;
              alu_op = OC8051_ALU_PCS;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP3;
              src_sel3 = OC8051_AS3_PC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_DJNZ_R : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_OP2;
              alu_op = OC8051_ALU_PCS;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP2;
              src_sel3 = OC8051_AS3_PC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_DJNZ_D : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_OP2;
              alu_op = OC8051_ALU_PCS;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP3;
              src_sel3 = OC8051_AS3_PC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_RET : begin
              ram_rd_sel = OC8051_RRS_SP;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_Y;
              pc_sel = OC8051_PIS_SP;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_RETI : begin
              ram_rd_sel = OC8051_RRS_SP;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_Y;
              pc_sel = OC8051_PIS_SP;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          default begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 =OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
          end
        endcase
        default: begin
        casex (op_in)
          OC8051_ACALL :begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_SP;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = 2'bxx;
              alu_op = OC8051_ALU_NOP;
              imm_sel = OC8051_IDS_PCL;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_Y;
              pc_sel = OC8051_PIS_I11;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_AJMP : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = 2'bxx;
              src_sel2 = 2'bxx;
              alu_op = 4'bxxxx;
              imm_sel = 2'bxx;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_Y;
              pc_sel = OC8051_PIS_I11;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_ADD_R : begin
          ram_rd_sel = OC8051_RRS_RN;
          ram_wr_sel = OC8051_RWS_ACC;
          src_sel1 = OC8051_ASS_ACC;
          src_sel2 = OC8051_ASS_RAM;
          alu_op = OC8051_ALU_ADD;
              wr = 1'b1;
          psw_set = OC8051_PS_AC;
          cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = 2'bxx;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_ADDC_R : begin
          ram_rd_sel = OC8051_RRS_RN;
          ram_wr_sel = OC8051_RWS_ACC;
          src_sel1 = OC8051_ASS_ACC;
          src_sel2 = OC8051_ASS_RAM;
          alu_op = OC8051_ALU_ADD;
              wr = 1'b1;
          psw_set = OC8051_PS_AC;
          cy_sel = OC8051_CY_PSW;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = 2'bxx;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_ANL_R : begin
              ram_rd_sel = OC8051_RRS_RN;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_RAM;
              alu_op = OC8051_ALU_AND;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = 2'bxx;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_CJNE_R : begin
              ram_rd_sel = OC8051_RRS_RN;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_RAM;
              alu_op = OC8051_ALU_SUB;
              wr = 1'b0;
              psw_set = OC8051_PS_CY;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP2;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_DEC_R : begin
              ram_rd_sel = OC8051_RRS_RN;
              ram_wr_sel = OC8051_RWS_RN;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_ZERO;
              alu_op = OC8051_ALU_SUB;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_1;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_DJNZ_R : begin
              ram_rd_sel = OC8051_RRS_RN;
              ram_wr_sel = OC8051_RWS_RN;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_ZERO;
              alu_op = OC8051_ALU_SUB;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_1;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = 2'bxx;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_INC_R : begin
              ram_rd_sel = OC8051_RRS_RN;
              ram_wr_sel = OC8051_RWS_RN;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_ZERO;
              alu_op = OC8051_ALU_ADD;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_1;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOV_R : begin
              ram_rd_sel = OC8051_RRS_RN;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end        OC8051_MOV_AR : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_RN;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOV_DR : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_RN;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOV_CR : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_RN;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP2;
              src_sel3 = OC8051_AS3_DC;
              comp_sel =OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOV_RD : begin
              ram_rd_sel = OC8051_RRS_RN;
              ram_wr_sel = OC8051_RWS_D;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_ORL_R : begin
              ram_rd_sel = OC8051_RRS_RN;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_OR;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_SUBB_R : begin
              ram_rd_sel =OC8051_RRS_RN;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_SUB;
              wr = 1'b1;
              psw_set = OC8051_PS_AC;
              cy_sel = OC8051_CY_PSW;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_XCH_R : begin
              ram_rd_sel = OC8051_RRS_RN;
              ram_wr_sel = OC8051_RWS_RN;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_XCH;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_1;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = 2'bxx;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_Y;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_XRL_R : begin
              ram_rd_sel = OC8051_RRS_RN;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 =OC8051_ASS_ACC;
              alu_op = OC8051_ALU_XOR;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
    //op_code [7:1]
          OC8051_ADD_I : begin
              ram_rd_sel = OC8051_RRS_I;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_RAM;
              alu_op = OC8051_ALU_ADD;
              wr = 1'b1;
              psw_set = OC8051_PS_AC;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = 2'bxx;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_ADDC_I : begin
              ram_rd_sel = OC8051_RRS_I;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_RAM;
              alu_op = OC8051_ALU_ADD;
              wr = 1'b1;
              psw_set = OC8051_PS_AC;
              cy_sel = OC8051_CY_PSW;
              pc_wr =OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = 2'bxx;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_ANL_I : begin
              ram_rd_sel = OC8051_RRS_I;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_RAM;
              alu_op = OC8051_ALU_AND;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = 2'bxx;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
         OC8051_CJNE_I : begin
              ram_rd_sel = OC8051_RRS_I;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_RAM;
              alu_op = OC8051_ALU_SUB;
              wr = 1'b0;
              psw_set = OC8051_PS_CY;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP2;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_DEC_I : begin
              ram_rd_sel = OC8051_RRS_I;
              ram_wr_sel = OC8051_RWS_I;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_ZERO;
              alu_op = OC8051_ALU_SUB;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_1;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_INC_I : begin
              ram_rd_sel = OC8051_RRS_I;
              ram_wr_sel = OC8051_RWS_I;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_ZERO;
              alu_op = OC8051_ALU_ADD;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_1;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOV_I : begin
              ram_rd_sel = OC8051_RRS_I;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOV_ID : begin
              ram_rd_sel = OC8051_RRS_I;
              ram_wr_sel = OC8051_RWS_D;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set =OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOV_AI : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_I;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOV_DI : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_I;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOV_CI : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_I;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP2;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOVX_IA : begin
              ram_rd_sel =OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_XRAM;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP2;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_RI;
            end
          OC8051_MOVX_AI :begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP2;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_RI;
            end
          OC8051_ORL_I : begin
              ram_rd_sel = OC8051_RRS_I;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_OR;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_SUBB_I : begin
              ram_rd_sel = OC8051_RRS_I;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_SUB;
              wr = 1'b1;
              psw_set = OC8051_PS_AC;
              cy_sel = OC8051_CY_PSW;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_XCH_I : begin
              ram_rd_sel = OC8051_RRS_I;
              ram_wr_sel = OC8051_RWS_I;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_XCH;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_1;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = 2'bxx;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_Y;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_XCHD :begin
              ram_rd_sel = OC8051_RRS_I;
              ram_wr_sel = OC8051_RWS_I;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_XCH;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = 2'bxx;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_Y;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_XRL_I : begin
              ram_rd_sel = OC8051_RRS_I;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_XOR;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
    //op_code [7:0]
          OC8051_ADD_D : begin
              ram_rd_sel =OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_RAM;
              alu_op = OC8051_ALU_ADD;
              wr = 1'b1;
              psw_set = OC8051_PS_AC;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = 2'bxx;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_ADD_C : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_ADD;
              wr = 1'b1;
              psw_set = OC8051_PS_AC;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP2;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_ADDC_D : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_RAM;
              alu_op = OC8051_ALU_ADD;
              wr = 1'b1;
              psw_set = OC8051_PS_AC;
              cy_sel = OC8051_CY_PSW;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = 2'bxx;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_ADDC_C : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_ADD;
              wr = 1'b1;
              psw_set = OC8051_PS_AC;
              cy_sel = OC8051_CY_PSW;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP2;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_ANL_D : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_RAM;
              alu_op = OC8051_ALU_AND;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = 2'bxx;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_ANL_C : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_AND;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP2;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_ANL_DD : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_D;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_RAM;
              alu_op = OC8051_ALU_AND;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = 2'bxx;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_ANL_DC : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_D;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_RAM;
              alu_op = OC8051_ALU_AND;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP3;
              src_sel3 = OC8051_AS3_DC;
              comp_sel =OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_ANL_B : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel =OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_AND;
              wr = 1'b0;
              psw_set = OC8051_PS_CY;
              cy_sel = OC8051_CY_PSW;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b1;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_ANL_NB : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_RR;
              wr = 1'b0;
              psw_set = OC8051_PS_CY;
              cy_sel = OC8051_CY_PSW;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b1;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_CJNE_D : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_SUB;
              wr = 1'b0;
              psw_set = OC8051_PS_CY;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_CJNE_C : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_SUB;
              wr = 1'b0;
              psw_set = OC8051_PS_CY;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel =OC8051_IDS_OP2;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_CLR_A : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_SUB;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel =OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_PC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_CLR_C : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_CY;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_PC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_CLR_B : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_D;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_PC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b1;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_CPL_A : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOT;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP3;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_CPL_C : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOT;
              wr = 1'b0;
              psw_set = OC8051_PS_CY;
              cy_sel = OC8051_CY_PSW;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP3;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_CPL_B : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_D;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOT;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_RAM;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP3;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b1;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_DA : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_DA;
              wr = 1'b1;
              psw_set = OC8051_PS_CY;
              cy_sel = OC8051_CY_DC;
              pc_wr =OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b1;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_DEC_A : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_ZERO;
              alu_op = OC8051_ALU_SUB;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_1;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 =OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_DEC_D : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_D;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_ZERO;
              alu_op = OC8051_ALU_SUB;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_1;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_DIV : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_B;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_RAM;
              alu_op = OC8051_ALU_DIV;
              wr = 1'b1;
              psw_set = OC8051_PS_OV;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_Y;
              rom_addr_sel =OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_DJNZ_D : begin
          ram_rd_sel = OC8051_RRS_D;
          ram_wr_sel = OC8051_RWS_D;
          src_sel1 = OC8051_ASS_RAM;
          src_sel2 = OC8051_ASS_ZERO;
          alu_op = OC8051_ALU_SUB;
              wr = 1'b1;
          psw_set = OC8051_PS_NOT;
          cy_sel = OC8051_CY_1;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = 2'bxx;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_INC_A : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_ZERO;
              alu_op = OC8051_ALU_ADD;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_1;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_INC_D : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_D;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_ZERO;
              alu_op = OC8051_ALU_ADD;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_1;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_INC_DP : begin
          ram_rd_sel = OC8051_RRS_D;
          ram_wr_sel = OC8051_RWS_DPTR;
          src_sel1 = OC8051_ASS_RAM;
          src_sel2 = OC8051_ASS_ZERO;
          alu_op = OC8051_ALU_ADD;
              wr = 1'b1;
          psw_set = OC8051_PS_NOT;
          cy_sel = OC8051_CY_1;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = 2'bxx;
              src_sel3 = OC8051_AS3_DP;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_JB : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_OP2;
              alu_op = OC8051_ALU_PCS;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP3;
              src_sel3 = OC8051_AS3_PC;
              comp_sel = OC8051_CSS_BIT;
              bit_addr = 1'b1;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_JBC :begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 =OC8051_ASS_OP2;
              alu_op = OC8051_ALU_PCS;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP3;
              src_sel3 = OC8051_AS3_PC;
              comp_sel = OC8051_CSS_BIT;
              bit_addr = 1'b1;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_JC : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_OP2;
              alu_op = OC8051_ALU_PCS;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel =OC8051_IDS_OP2;
              src_sel3 = OC8051_AS3_PC;
              comp_sel = OC8051_CSS_CY;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_JMP : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_RAM;
              alu_op = OC8051_ALU_ADD;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DP;
              comp_sel = OC8051_CSS_BIT;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_JNB : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_OP2;
              alu_op = OC8051_ALU_PCS;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP3;
              src_sel3 = OC8051_AS3_PC;
              comp_sel = OC8051_CSS_BIT;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_JNC : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_OP2;
              alu_op = OC8051_ALU_PCS;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP2;
              src_sel3 = OC8051_AS3_PC;
              comp_sel = OC8051_CSS_CY;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_JNZ :begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_OP2;
              alu_op = OC8051_ALU_PCS;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP2;
              src_sel3 = OC8051_AS3_PC;
              comp_sel = OC8051_CSS_AZ;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_JZ : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_OP2;
              alu_op = OC8051_ALU_PCS;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP2;
              src_sel3 = OC8051_AS3_PC;
              comp_sel = OC8051_CSS_AZ;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_LCALL :begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_SP;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = 2'bxx;
              alu_op = OC8051_ALU_NOP;
              imm_sel = OC8051_IDS_PCL;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_Y;
              pc_sel = OC8051_PIS_I16;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_LJMP : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = 2'bxx;
              src_sel2 = 2'bxx;
              alu_op = 4'bxxxx;
              imm_sel = 2'bxx;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_Y;
              pc_sel = OC8051_PIS_I16;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOV_D : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 =OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOV_C : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP2;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOV_DA : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_D;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOV_DD : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_D3;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP2;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOV_CD : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_D;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP3;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOV_BC : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 =OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_CY;
              cy_sel = OC8051_CY_RAM;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel =OC8051_CSS_DC;
              bit_addr = 1'b1;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOV_CB : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_D;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_PSW;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP3;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b1;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOV_DP : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DPTR;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_OP2;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP3;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOVC_DP :begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_RAM;
              alu_op = OC8051_ALU_ADD;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = 2'bxx;
              src_sel3 = OC8051_AS3_DP;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOVC_PC : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_OP2;
              alu_op = OC8051_ALU_ADD;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel =OC8051_PIS_DC;
              imm_sel = 2'bxx;
              src_sel3 = OC8051_AS3_DP;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_MOVX_PA : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_XRAM;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel =OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP2;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DPTR;
            end
          OC8051_MOVX_AP : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_XRAM;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DPTR;
            end
          OC8051_MUL : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_B;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_RAM;
              alu_op = OC8051_ALU_MUL;
              wr = 1'b1;
              psw_set = OC8051_PS_OV;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_Y;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
         OC8051_ORL_D : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_OR;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel =OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_ORL_C : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_OR;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP2;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_ORL_AD : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_D;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_OR;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_ORL_CD : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_D;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_RAM;
              alu_op = OC8051_ALU_OR;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP3;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_ORL_B : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_OR;
              wr = 1'b0;
              psw_set = OC8051_PS_CY;
              cy_sel = OC8051_CY_PSW;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b1;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_ORL_NB : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_RL;
              wr = 1'b0;
              psw_set = OC8051_PS_CY;
              cy_sel = OC8051_CY_PSW;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b1;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_POP : begin
              ram_rd_sel = OC8051_RRS_SP;
              ram_wr_sel = OC8051_RWS_D;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_PUSH : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_SP;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_RET : begin
              ram_rd_sel = OC8051_RRS_SP;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_RETI : begin
              ram_rd_sel = OC8051_RRS_SP;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_RL : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_RL;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_RLC : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_RLC;
              wr = 1'b1;
              psw_set = OC8051_PS_CY;
              cy_sel = OC8051_CY_PSW;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_RR : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_RR;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr =OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_RRC : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 =OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_RRC;
              wr = 1'b1;
              psw_set = OC8051_PS_CY;
              cy_sel = OC8051_CY_PSW;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel =OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_SETB_C : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b0;
              psw_set = OC8051_PS_CY;
              cy_sel = OC8051_CY_1;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_PC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel =OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_SETB_B : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_D;
              src_sel1 = OC8051_ASS_DC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_NOP;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_1;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_PC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b1;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_SJMP : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_OP2;
              alu_op = OC8051_ALU_PCS;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP2;
              src_sel3 = OC8051_AS3_PC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_SUBB_D : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_SUB;
              wr = 1'b1;
              psw_set = OC8051_PS_AC;
              cy_sel = OC8051_CY_PSW;
              pc_wr = OC8051_PCW_N;
              pc_sel =OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel =OC8051_EAS_DC;
            end
          OC8051_SUBB_C : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_SUB;
              wr = 1'b1;
              psw_set = OC8051_PS_AC;
              cy_sel = OC8051_CY_PSW;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP2;
              src_sel3 =OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_SWAP : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = OC8051_ASS_ACC;
              src_sel2 = OC8051_ASS_DC;
              alu_op = OC8051_ALU_RLC;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_Y;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_XCH_D : begin
              ram_rd_sel =OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_D;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_XCH;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_1;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = 2'bxx;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_Y;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_XRL_D : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel =OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_XOR;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel =OC8051_EAS_DC;
            end
          OC8051_XRL_C : begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_ACC;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_XOR;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP2;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_XRL_AD : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_D;
              src_sel1 = OC8051_ASS_RAM;
              src_sel2 = OC8051_ASS_ACC;
              alu_op = OC8051_ALU_XOR;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr =OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          OC8051_XRL_CD : begin
              ram_rd_sel = OC8051_RRS_D;
              ram_wr_sel = OC8051_RWS_D;
              src_sel1 = OC8051_ASS_IMM;
              src_sel2 = OC8051_ASS_RAM;
              alu_op = OC8051_ALU_XOR;
              wr = 1'b1;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              imm_sel = OC8051_IDS_OP3;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
            end
          default: begin
              ram_rd_sel = OC8051_RRS_DC;
              ram_wr_sel = OC8051_RWS_DC;
              src_sel1 = 2'bxx;
              src_sel2 = 2'bxx;
              alu_op = OC8051_ALU_NOP;
              imm_sel = 2'bxx;
              wr = 1'b0;
              psw_set = OC8051_PS_NOT;
              cy_sel = OC8051_CY_0;
              pc_wr = OC8051_PCW_N;
              pc_sel = OC8051_PIS_DC;
              src_sel3 = OC8051_AS3_DC;
              comp_sel = OC8051_CSS_DC;
              bit_addr = 1'b0;
              wad2 = OC8051_WAD_N;
              rom_addr_sel = OC8051_RAS_PC;
              ext_addr_sel = OC8051_EAS_DC;
           end
        endcase
        end
        endcase
      end
    end
    //
    // remember current instruction
    always @(posedge clk)
      if (state==2'b00)
        op <= #1 op_in;
    //
    // in case of instructions that needs more than one clock set state
    always @(posedge clk or posedge rst)
    begin
      if (rst)
        state <= #1 1'b0;
      else begin
        case (state)
          2'b00: begin
            casex (op_in)
              OC8051_ACALL :state <= #1 2'b01;
              OC8051_AJMP : state <= #1 2'b01;
              OC8051_CJNE_R :state <= #1 2'b11;
              OC8051_CJNE_I :state <= #1 2'b11;
              OC8051_CJNE_D : state <= #1 2'b11;
              OC8051_CJNE_C : state <= #1 2'b11;
              OC8051_LJMP : state <= #1 2'b01;
              OC8051_DJNZ_R :state <= #1 2'b11;
              OC8051_DJNZ_D :state <= #1 2'b11;
              OC8051_LCALL :state <= #1 2'b01;
              OC8051_MOVC_DP :state <= #1 2'b10;
              OC8051_MOVC_PC :state <= #1 2'b10;
              OC8051_RET : state <= #1 2'b11;
              OC8051_RETI : state <= #1 2'b11;
              OC8051_SJMP : state <= #1 2'b10;
              OC8051_JB : state <= #1 2'b10;
              OC8051_JBC : state <= #1 2'b10;
              OC8051_JC : state <= #1 2'b10;
              OC8051_JMP : state <= #1 2'b10;
              OC8051_JNC : state <= #1 2'b10;
              OC8051_JNB : state <= #1 2'b10;
              OC8051_JNZ : state <= #1 2'b10;
              OC8051_JZ : state <= #1 2'b10;
              default: state <= #1 2'b00;
            endcase
          end
          2'b01: state <= #1 2'b00;
          2'b10: state <= #1 2'b01;
          2'b11: state <= #1 2'b10;
          default: state <= #1 2'b00;
        endcase
      end
    end
    //
    //in case of reti
    always @(posedge clk)
      if (op==OC8051_RETI) reti <= #1 1'b1;
      else reti <= #1 1'b0;
    //
    //in case of writing to external ram
    always @(op_in or rst or rd)
    begin
      if (rst)
        write_x = 1'b0;
      else if (rd)
      begin
        casex (op_in)
          OC8051_MOVX_AI : write_x = 1'b1;
          OC8051_MOVX_AP : write_x = 1'b1;
          default : write_x = 1'b0;
        endcase
      end else write_x = 1'b0;
    end
    endmodule
     

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