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Counting sequence

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digitalp

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The 4-bit counter is a counter which counts as 0,1,1,2,3,5,8,13,0,1,1,2,3,5,....
Implement a multiple mode counter which can count up (MODE=00),count down (MODE =01) and count up (MODE =10 ).
MODE is a 2 bit DIP switch.
RESET push button reset the counter.

Components provided:
DIP switch
LEDs
SN74LS191N sync. 4-bit up/down counter with mode control
HD74LS283P 4 bit bib=nary adder
HD74LS48P BCD to 7 segment decoder
DM74LS157N quad 2 to 1 line data selector/multiplexer
HD74LS194AP 4-bit universal bi-directional shift register

How to start this project? Schematics diagram,need guidance. Any other additional components needed?
Not a must to use all the components provided.
I need help esp. schematics diagram for connection in the breadboard?
 
Last edited:
Sounds like homework, which should be in the homework section. Here's some info to start.
 
Yes, you can have help but we won't do the work for you. You need to make an attempt to draw the schematic and then ask to have it checked.
 
Hi,

The way i would do this is to use a single counter with limited states, then decode the output into the correct required states.
There are other interesting ways to do this too though.

The simplest is to use a counter and 4x4 bit ROM (256 memory bits total). The ROM is programmed so that when the normal counter state appears on the address lines, the data output is the correct Fibonacci code. So 0 decodes to 0, 1 decodes to 1, 2 decodes to 1, 3 decodes to 2, 4 decodes to 3, 5 decodes to 5, 6 decodes to 8, 7 decodes to 13. If 13 is the actual last number then we could do this with less memory too.
This can also be done with logic gates.
 
Here is another student I would just love to hire after he/she graduates NOT!
 
I have 74138 (3 to 8 line decoder/ demultiplexer)

Hello again,

What else do you have to work with, such as AND or NAND gates, OR or NOR gates, XOR gates, INVERTER, etc. ?
Can you use programmable memory?
 
Have you studied Mealy and Moore state machines? This problem can be solved using these principles.

Hint: Note that there only eight states, where state7 recycles back to state0 if counting up (and state7 back to state0 if counting down). A four-bit binary up/down counter knows how to do this with no added logic...
 
Have you studied Mealy and Moore state machines? This problem can be solved using these principles.

Hint: Note that there only eight states, where state7 recycles back to state0 if counting up (and state7 back to state0 if counting down). A four-bit binary up/down counter knows how to do this with no added logic...
No, I didn't learn about it. I am only supposed to use logic gates, build the circuit on the breadboard.
 
I can't use programmable memory. use logic gates to do. I have e.g.
SN74LS191N sync. 4-bit up/down counter with mode control
HD74LS283P 4 bit binary adder
HD74LS48P BCD to 7 segment decoder
DM74LS157N quad 2 to 1 line data selector/multiplexer
HD74LS194AP 4-bit universal bi-directional shift register
I have 74138 (3 to 8 line decoder/ demultiplexer)
and such such as AND or NAND gates, OR or NOR gates, XOR gates, INVERTER..so on.

Is it use counters' input into decoder and then output into the encoder?
how do the part where the sequence from 13 then goes back to 0?
Still unsure which pins to connect to?


Hello again,

The circuit would look like this...

Use the counter counting UP. Using outputs A,B, and C, ignore D. So now A is LSB and C is MSB. Doing this means that the count will repeat without doing anything else.

Run those three outputs to the 74LS138 chip. You'll also have to look at the data sheet to see which other inputs have to be set to allow the 74LS138 to be enabled all the time. That's part of your job.

The outputs of the 74LS138 are inverted, but we'll call them y0, y1, y2, etc., up to y7. All the outputs are high except for the one who's inputs to the device are that outputs binary code, so when the counter is in state 0000 binary, only the y0 output of the 74LS138 is low, and when the counter is in state 0001 binary, only the y1 output is low, etc., so when the counter is in state 0111 binary, only the y7 output of the 74LS138 decoder is low.
So we have all 8 possible states decoded into a single output line with the 74LS138.

Next, we use NAND gates to generate the output code, which will be in the format you want. I'll use 8 input NAND gates and leave it to you to simplify this by using less input gates if you can. That gives you something to think about too. 8 input NAND gates would represent the solution for the most extreme problem, but this isnt that, so you should be able to reduce the number of inputs needed for the NAND gates to get the right output.

Ok, so we have the counter counting 0 to 15 and back again, but we're only using outputs A, B, and C, so the count to the decoder is only 0 to 7 and back again to zero. Those outputs will feed the NAND gates, and the output of the NAND gates will give us the required codes.

To make the NAND gates output the correct code, we look at the required state mapping:
0:0:0000
1:1:0001
2:1:0001
3:2:0010
4:3:0011
5:5:0101
6:8:1000
7:13:1011

The above is arranged in order of the counter's count, the required output, and the required output in binary:
counter:required_output:required_output_in_binary

On the output we have four 8 input NAND gates (for now), so the last thing we have to do is decide which of the 8 outputs of the decoder go to which NAND gate inputs. The four NAND gate outputs create the four bit output, bit 0, bit 1, bit 2, and bit 3, one NAND gate for each bit. bit 0 is the LSB output and bit 3 is the MSB output.

To start, a count of 0 maps to an output of 0000, so that means output y0 doesnt connect to anything because with no inputs to the NAND gates (assuming all unused inputs pulled high) the output state is 0000 also.
Next, a count of 1 maps to an output of 0001, so that means y1 connects to an input of the LSB NAND gate (bit 0). This means when the counter is in state 0001 the output is also 0001.
Next, a count of 2 maps to an output of 0001, so that means y2 connects to a second input of the LSB NAND bit 0 gate. This means when the counter is in state 0010 the output is also 0001.
Next, a count of 3 maps to an output of 0010, so that means y3 connects to an input of the next NAND gate (bit 1). This means when the counter is in state 0011 the output state is 0010.
Next, a count of 4 maps to an output of 0011, so that means y4 connects to an unused input of the bit 0 NAND gate and also to an unused input of the bit 1 NAND gate, so that when the count 4 appears on the counter we get both output bits 0 and 1 high, for a code of 0011.

So following that pattern, we get the required output codes. When the counter gets to 7 it goes back to 0 so we get the same thing again without having to manually reset the counter.

See if you can follow that procedure, and see if you can reduce the number of inputs required for each NAND gate as well as the total number of NAND gates required for this solution. You should be able to do both.
Draw up the circuit and post here and we can take a look.
 
Last edited:
Hello again,

The circuit would look like this...

Use the counter counting UP. Using outputs A,B, and C, ignore D. So now A is LSB and C is MSB. Doing this means that the count will repeat without doing anything else.

Run those three outputs to the 74LS138 chip. You'll also have to look at the data sheet to see which other inputs have to be set to allow the 74LS138 to be enabled all the time. That's part of your job.

The outputs of the 74LS138 are inverted, but we'll call them y0, y1, y2, etc., up to y7. All the outputs are high except for the one who's inputs to the device are that outputs binary code, so when the counter is in state 0000 binary, only the y0 output of the 74LS138 is low, and when the counter is in state 0001 binary, only the y1 output is low, etc., so when the counter is in state 0111 binary, only the y7 output of the 74LS138 decoder is low.
So we have all 8 possible states decoded into a single output line with the 74LS138.

Next, we use NAND gates to generate the output code, which will be in the format you want. I'll use 8 input NAND gates and leave it to you to simplify this by using less input gates if you can. That gives you something to think about too. 8 input NAND gates would represent the solution for the most extreme problem, but this isnt that, so you should be able to reduce the number of inputs needed for the NAND gates to get the right output.

Ok, so we have the counter counting 0 to 15 and back again, but we're only using outputs A, B, and C, so the count to the decoder is only 0 to 7 and back again to zero. Those outputs will feed the NAND gates, and the output of the NAND gates will give us the required codes.

To make the NAND gates output the correct code, we look at the required state mapping:
0:0:0000
1:1:0001
2:1:0001
3:2:0010
4:3:0011
5:5:0101
6:8:1000
7:13:1011

The above is arranged in order of the counter's count, the required output, and the required output in binary:
counter:required_output:required_output_in_binary

On the output we have four 8 input NAND gates (for now), so the last thing we have to do is decide which of the 8 outputs of the decoder go to which NAND gate inputs. The four NAND gate outputs create the four bit output, bit 0, bit 1, bit 2, and bit 3, one NAND gate for each bit. bit 0 is the LSB output and bit 3 is the MSB output.

To start, a count of 0 maps to an output of 0000, so that means output y0 doesnt connect to anything because with no inputs to the NAND gates (assuming all unused inputs pulled high) the output state is 0000 also.
Next, a count of 1 maps to an output of 0001, so that means y1 connects to an input of the LSB NAND gate (bit 0). This means when the counter is in state 0001 the output is also 0001.
Next, a count of 2 maps to an output of 0001, so that means y2 connects to a second input of the LSB NAND bit 0 gate. This means when the counter is in state 0010 the output is also 0010.
Next, a count of 3 maps to an output of 0010, so that means y3 connects to an input of the next NAND gate (bit 1). This means when the counter is in state 0011 the output state is 0010.
Next, a count of 4 maps to an output of 0011, so that means y4 connects to an unused input of the bit 0 NAND gate and also to an unused input of the bit 1 NAND gate, so that when the count 4 appears on the counter we get both output bits 0 and 1 high, for a code of 0011.

So following that pattern, we get the required output codes. When the counter gets to 7 it goes back to 0 so we get the same thing again without having to manually reset the counter.

See if you can follow that procedure, and see if you can reduce the number of inputs required for each NAND gate as well as the total number of NAND gates required for this solution. You should be able to do both.
Draw up the circuit and post here and we can take a look.
 
Thanks a lot.

Do I need to use encoder 74LS148?
Hello again,

The circuit would look like this...

Use the counter counting UP. Using outputs A,B, and C, ignore D. So now A is LSB and C is MSB. Doing this means that the count will repeat without doing anything else.

Run those three outputs to the 74LS138 chip. You'll also have to look at the data sheet to see which other inputs have to be set to allow the 74LS138 to be enabled all the time. That's part of your job.

The outputs of the 74LS138 are inverted, but we'll call them y0, y1, y2, etc., up to y7. All the outputs are high except for the one who's inputs to the device are that outputs binary code, so when the counter is in state 0000 binary, only the y0 output of the 74LS138 is low, and when the counter is in state 0001 binary, only the y1 output is low, etc., so when the counter is in state 0111 binary, only the y7 output of the 74LS138 decoder is low.
So we have all 8 possible states decoded into a single output line with the 74LS138.

Next, we use NAND gates to generate the output code, which will be in the format you want. I'll use 8 input NAND gates and leave it to you to simplify this by using less input gates if you can. That gives you something to think about too. 8 input NAND gates would represent the solution for the most extreme problem, but this isnt that, so you should be able to reduce the number of inputs needed for the NAND gates to get the right output.

Ok, so we have the counter counting 0 to 15 and back again, but we're only using outputs A, B, and C, so the count to the decoder is only 0 to 7 and back again to zero. Those outputs will feed the NAND gates, and the output of the NAND gates will give us the required codes.

To make the NAND gates output the correct code, we look at the required state mapping:
0:0:0000
1:1:0001
2:1:0001
3:2:0010
4:3:0011
5:5:0101
6:8:1000
7:13:1011

The above is arranged in order of the counter's count, the required output, and the required output in binary:
counter:required_output:required_output_in_binary

On the output we have four 8 input NAND gates (for now), so the last thing we have to do is decide which of the 8 outputs of the decoder go to which NAND gate inputs. The four NAND gate outputs create the four bit output, bit 0, bit 1, bit 2, and bit 3, one NAND gate for each bit. bit 0 is the LSB output and bit 3 is the MSB output.

To start, a count of 0 maps to an output of 0000, so that means output y0 doesnt connect to anything because with no inputs to the NAND gates (assuming all unused inputs pulled high) the output state is 0000 also.
Next, a count of 1 maps to an output of 0001, so that means y1 connects to an input of the LSB NAND gate (bit 0). This means when the counter is in state 0001 the output is also 0001.
Next, a count of 2 maps to an output of 0001, so that means y2 connects to a second input of the LSB NAND bit 0 gate. This means when the counter is in state 0010 the output is also 0010.
Next, a count of 3 maps to an output of 0010, so that means y3 connects to an input of the next NAND gate (bit 1). This means when the counter is in state 0011 the output state is 0010.
Next, a count of 4 maps to an output of 0011, so that means y4 connects to an unused input of the bit 0 NAND gate and also to an unused input of the bit 1 NAND gate, so that when the count 4 appears on the counter we get both output bits 0 and 1 high, for a code of 0011.

So following that pattern, we get the required output codes. When the counter gets to 7 it goes back to 0 so we get the same thing again without having to manually reset the counter.

See if you can follow that procedure, and see if you can reduce the number of inputs required for each NAND gate as well as the total number of NAND gates required for this solution. You should be able to do both.
Draw up the circuit and post here and we can take a look.
 
Last edited:
I have uploaded the schematic diagram.

Hello again,

The circuit would look like this...

Use the counter counting UP. Using outputs A,B, and C, ignore D. So now A is LSB and C is MSB. Doing this means that the count will repeat without doing anything else.

Run those three outputs to the 74LS138 chip. You'll also have to look at the data sheet to see which other inputs have to be set to allow the 74LS138 to be enabled all the time. That's part of your job.

The outputs of the 74LS138 are inverted, but we'll call them y0, y1, y2, etc., up to y7. All the outputs are high except for the one who's inputs to the device are that outputs binary code, so when the counter is in state 0000 binary, only the y0 output of the 74LS138 is low, and when the counter is in state 0001 binary, only the y1 output is low, etc., so when the counter is in state 0111 binary, only the y7 output of the 74LS138 decoder is low.
So we have all 8 possible states decoded into a single output line with the 74LS138.

Next, we use NAND gates to generate the output code, which will be in the format you want. I'll use 8 input NAND gates and leave it to you to simplify this by using less input gates if you can. That gives you something to think about too. 8 input NAND gates would represent the solution for the most extreme problem, but this isnt that, so you should be able to reduce the number of inputs needed for the NAND gates to get the right output.

Ok, so we have the counter counting 0 to 15 and back again, but we're only using outputs A, B, and C, so the count to the decoder is only 0 to 7 and back again to zero. Those outputs will feed the NAND gates, and the output of the NAND gates will give us the required codes.

To make the NAND gates output the correct code, we look at the required state mapping:
0:0:0000
1:1:0001
2:1:0001
3:2:0010
4:3:0011
5:5:0101
6:8:1000
7:13:1011

The above is arranged in order of the counter's count, the required output, and the required output in binary:
counter:required_output:required_output_in_binary

On the output we have four 8 input NAND gates (for now), so the last thing we have to do is decide which of the 8 outputs of the decoder go to which NAND gate inputs. The four NAND gate outputs create the four bit output, bit 0, bit 1, bit 2, and bit 3, one NAND gate for each bit. bit 0 is the LSB output and bit 3 is the MSB output.

To start, a count of 0 maps to an output of 0000, so that means output y0 doesnt connect to anything because with no inputs to the NAND gates (assuming all unused inputs pulled high) the output state is 0000 also.
Next, a count of 1 maps to an output of 0001, so that means y1 connects to an input of the LSB NAND gate (bit 0). This means when the counter is in state 0001 the output is also 0001.
Next, a count of 2 maps to an output of 0001, so that means y2 connects to a second input of the LSB NAND bit 0 gate. This means when the counter is in state 0010 the output is also 0010.
Next, a count of 3 maps to an output of 0010, so that means y3 connects to an input of the next NAND gate (bit 1). This means when the counter is in state 0011 the output state is 0010.
Next, a count of 4 maps to an output of 0011, so that means y4 connects to an unused input of the bit 0 NAND gate and also to an unused input of the bit 1 NAND gate, so that when the count 4 appears on the counter we get both output bits 0 and 1 high, for a code of 0011.

So following that pattern, we get the required output codes. When the counter gets to 7 it goes back to 0 so we get the same thing again without having to manually reset the counter.

See if you can follow that procedure, and see if you can reduce the number of inputs required for each NAND gate as well as the total number of NAND gates required for this solution. You should be able to do both.
Draw up the circuit and post here and we can take a look.
 

Attachments

  • Counter_decoder_nand.png
    Counter_decoder_nand.png
    161.6 KB · Views: 496
Hi,

Well you are going to have to explain what that schematic is because that bares no resemblance to the schematic i suggested. What i suggested was a neat and orderly process to obtain the correct output codes. What that schematic looks like is a mess of connections and i dont even see where the outputs are. So maybe you could explain a little about what you were trying to do there.

The schematic i was talking about is partially drawn in the attachment which shows only the basic parts not all the interconnections.
 

Attachments

  • Counter_decoder_nand.gif
    Counter_decoder_nand.gif
    19.3 KB · Views: 435
Last edited:
A "data selector/mux" makes it easy to "cheat". It's a great way to eliminate lots of logic.

With the chip supplied you "could", for instance change some value to anything you wanted to with one bit for the input. e.g. something like the input is unchanged or fixed at some value.
 
Here's more clues. To be exact, you need a 5-input NAND gate and 3 dual-input NAND. I have removed all the interconnecting wires between the 74138 outputs and the NAND gate inputs for you to fill in.

If you read Mr AL's reply closely, you'll find all the informations needed to plot the wires here

Mr Al said:
To make the NAND gates output the correct code, we look at the required state mapping:
0:0:0000
1:1:0001
2:1:0001
3:2:0010
4:3:0011
5:5:0101
6:8:1000
7:13:1011

Allen
 

Attachments

  • counter_clue.PNG
    counter_clue.PNG
    37.6 KB · Views: 596
Hi,

Well you are going to have to explain what that schematic is because that bares no resemblance to the schematic i suggested. What i suggested was a neat and orderly process to obtain the correct output codes. What that schematic looks like is a mess of connections and i dont even see where the outputs are. So maybe you could explain a little about what you were trying to do there.

The schematic i was talking about is partially drawn in the attachment which shows only the basic parts not all the interconnections.
For 0001: Y1 connected to pin A 0f bit 0.
For 0001: Y2 connected to pin B 0f bit 0.
For 0010: Y3 connected to pin A 0f bit 1.
......
 

Attachments

  • counter_v1.png
    counter_v1.png
    23.4 KB · Views: 673
Last edited:
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