I'm having serious problems configuring my FPGA using EPC2. We have
designed the circuit exactly as stated in the Altera datasheet and
even played around with the pullups and buffering that's recommended.
To be more specific, We have a board with a FLEX10KE
(EPF10K200SBC356-1) and a EPC2LC20 for in-system configuration. We
also have provided for direct Byteblaster configuration using a
connector (using the same path towards the FPGA and selecting between
them through enabling/disabling a buffer). Finally, we have a JTAG
connector by which we can configure the FPGA directly using the SOF
file generated by Quartus - this works fine. I won't go into more details at this point, because it gets too specific. If anyone has any experience on the matter please get in touch and I will tell exactly what is happening.
Thanks
designed the circuit exactly as stated in the Altera datasheet and
even played around with the pullups and buffering that's recommended.
To be more specific, We have a board with a FLEX10KE
(EPF10K200SBC356-1) and a EPC2LC20 for in-system configuration. We
also have provided for direct Byteblaster configuration using a
connector (using the same path towards the FPGA and selecting between
them through enabling/disabling a buffer). Finally, we have a JTAG
connector by which we can configure the FPGA directly using the SOF
file generated by Quartus - this works fine. I won't go into more details at this point, because it gets too specific. If anyone has any experience on the matter please get in touch and I will tell exactly what is happening.
Thanks
