Clock speed

[Parth86]

hello,
I have some query
Processor need fixed number of clock or cycle to execute instruction. I think different instruction take different cycle to execute. some instruction take one cycle, some instruction take two cycle

Q1 the speed of processor depend on which parameter (data bit or address bit) ?
Q2 can we choose any crystal for any mircocontroller (PIC, 8051,) ?

 

[MikeMl]

The instructions that take more time are usually the ones where you have to do additional memory cycles or bank switching to fetch operands. For the short instructions, all of the data is already available either in the instruction word, or in the ALU.

Not any crystal. There is always a spec for the highest allowed frequency, and sometimes for the lowest allowed frequency. The type of crystal, fundamental, overtone, series-resonant, parallel-resonant, load capacitance, or no crystal (replace with RC network) is specified on the microprocessor's Data Sheet.

When in doubt, download, and study the data sheet.

 

[Parth86]

I am reading this paragraph. I am trying to understand some basic. There is not enough explanation so I am asking here

Single-cycle processors suffer from poor speed performance. Control and data signals must propagate completely
through the processor in a single cycle, which means that cycle times need to be long, and many parts of the
hardware tend to be dormant for much of the cycle.
Multi-Cycle Stages =
Multi-cycle processors break up the instruction into its fundamental parts, and executes each part of the instruction in
a different clock cycle. Since signals have less distance to travel in a single cycle, the cycle times can be sped up
considerably.
Typically, an instruction is executed over at least 5 cycles, which are named as such:
IF
Fetch the instruction from memory
ID
Decode the instruction, and generate the necessary control signals
EX
Feed the necessary control signals into the ALU and produce a result
MEM
Read from memory, if specified
WB
Write the result back to the register file or to memory.

1Fetch the instruction from memory
my explanation: read the program memory and store the instruction in instruction register.we need to component only
program memory and instruction register

2.Decode the instruction, and generate the necessary control signals
my explanation: 8 bit instruction
ADD A,R1
4 bit for opcode like ADD, SUB, INC, ...
4 bit for control signal like A, R1

I don't understand last three instruction?

 

[KeepItSimpleStupid]

Remember there is RISC and CISC architectures. The sequence is generally Fetch, Decode and Execute with the PC pointing to the next instruction when complete.
CISC architectures may require more than one cycle. e.g. ADD #A, (R1+)

 

[Parth86]

Remember there is RISC and CISC architectures. The sequence is generally Fetch, Decode and Execute with the PC pointing to the next instruction when complete.
CISC architectures may require more than one cycle. e.g. ADD #A, (R1+)

CISC chips have an increasing number of components and an ever increasing instruction set and so are always slower and less powerful at executing “common” instructions. CISC chips execute an instruction in two to ten machine cycles

RISC chips have fewer components and a smaller instruction set, allowing faster accessing of “common” instructions
RISC chips execute an instruction in one machine cycle
look this picture. this can executed three instruction
MOV A,#immediate data
MOV A, R1
MOV R1,A

MOV A,#immediate data
MOV A, R1
MOV R1,A
how many cycle I need to execute these instruction?. I think ,two because I don't need to decode signal. to execute the instruction we can fetch and directly execute instruction

 

[KeepItSimpleStupid]

I cycle to be a fetch/decode/execute CYCLE. Not saying hat rising edge, could be fetch, the flat top decode and the trailing edge execute or three separate clock cycles.

Each take time:
Fetch: RAM/CORE/SWAP/CACHE take different times
Decode: is largely logic probigation
Execute: Probably in RISC it's shorter.

 

[Parth86]

I cycle to be a fetch/decode/execute CYCLE. Not saying hat rising edge, could be fetch, the flat top decode and the trailing edge execute or three separate clock cycles.

Each take time:
Fetch: RAM/CORE/SWAP/CACHE take different times
Decode: is largely logic probigation
Execute: Probably in RISC it's shorter.

please check capability of circuit.
can we execute following instruction with this circuit
load ,store ,arithmetic and logic instruction

Note : I did not use 2 input 4 bit logic Ics. I don't have this Ic in software
How to improve circuit ?

 

[Parth86]

please check capability of circuit.
can we execute following instruction with this circuit
load ,store ,arithmetic and logic instruction
View attachment 90063

Note : I did not use 2 input 4 bit logic Ics. I don't have this Ic in software
How to improve circuit ?

please help me , whats wrong with that circuit. just tell me few mistakes. I will modify the circuit. please help me