3-bit synchronous binary up/down counter J-K flip flops

[center15]

Hello everyone, I got an project which is about design 3-bit synchronous binary up/down counter with BCD display. The counter will produce the (up) sequence 0,1,3,5,7,0,1,3,...(repeats) or (down) sequence 0,7,5,3,1,0,7,5,3,1,...(re-peats).

I got problem on counter which presents 0,1,3,5,7 , Can anyone tell me how to present these squences? any truth table or logic diagram please? thank you

 

[Grossel]

What about making a regular counter, and then using just simple boolean logic to get your own sequence?

 

[MikeMl]

Is this Homework?

 

[Vizier87]

probably a Cedar assignment.

 

[Grossel]

non-english

probably a Cedar assignment.

What is that?

 

[Vizier87]

Simulation of logic/sequential circuits by the software of the name Cedar.

 

[alexrandallus]

hi can you please help me to design a 5bit binary up counter using t flip flop... the output that would be display are odd nos from 0-20 meaning the counting will start at 1,3,5,7 to 19.. and will reset again... a nice state diagram and logic diagram will really help a lot..

 

[Grossel]

hi can you please help me to design a 5bit binary up counter using t flip flop... the output that would be display are odd nos from 0-20 meaning the counting will start at 1,3,5,7 to 19.. and will reset again... a nice state diagram and logic diagram will really help a lot..

Ask thread starter. You two should collaborate about this task as your question is very similar to tread starters question.

Hint: The number of ekstra logic gates will increase rapidly as you add more step to your counter because the inputs on the gates also increases with number of bits.

Nice results for you from a simple google search:
Synchronous counter (JK flipflops)
**broken link removed**

 

[SLACer]

t-ff odd counter

The attachment is the T-flip-flop counter design. I used a logic simulator called Max II from Altera Corp. It is a free download. I highly recommend it for anyone. I believe it is simpler to learn, and use than most of the offerings from other sources. a perfect vehicle for begging VHDL
Note: in this design, I did not further reduce the logic from the original K-maps. I will leave that to the reader.