Does anyone know of a reliable way to interface to a 4Mbit or more Flash memory chip up to using only 8 I/O lines?

From my literature review, it appears to be feasible..but I just want to bounce around the idea around 1st.

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There are no perfect solutions, only solutions acceptable for the times

 

Atmels dataflash uses SPI which can be as low as 3 lines - its not a parallel bus though. Most parralel flash has an 8 bit bus you need at least 11 lines (8 data/address lines and 3 control lines). You could work out a multiplexing scheme but it probably wouldn't be that much faster than just using SPI.

Brent