Perhaps you had better let us know what you are trying to do?, there may be a simpler way?.

Certainly if you are introducing lots more requirements you are likely to start running short of cycles.

An incremental encoder normally has two outputs with the ff. sequence

output1 - 0110011001100110.....
output2 - 0011001100110011.....

When a switch is ON, the sequence is reversed

output1 - 0011001100110011.....
output2 - 0110011001100110.....

In addition, you want the encoder to step through the sequence at a rate adjustable from 0Hz to 50Khz in 50Hz steps. The adjustment is through an an analog voltage input. Is this what you need?

This is doable except that at the highest frequecies, the speed adjustment may not be smooth. That is, changing the speed from 49050Hz to 50000Hz might not be easily done.

Let me outline the solution I have in mind. There are two parts to the program. The first part is generating the encoder sequence at a set frequency. The second part is reading from an analog input, perform A/D conversion, and translating the result to a frequency setting used in the first part.

The way to generate the sequence is through interrupts. 50Khz is a relatively high rate and a 20Mhz PIC16F628 should give you enough headroom. The ff. steps are needed to setup:

a. Setup CCP1CON register for "compare mode, trigger special event". I.E., initialize CCP1CON to 00001011B.
b. Initialize TMR1CON with the value 00010001 (TMR1ON and 1:2 prescale). This will supply a 2.5Mhz clock to TMR1 from a 20Mhz oscillator.
c. Initialize CCPR1H,CCPR1L with the value 50. This will give an initial interrupt rate of 50KHz. To get an interrupt rate of 50Hz, the registers should be intialized to 50. To get a specific frequency, a suitable value from 50-50,000 should be entered. Notice there are 1000 values. A lookup table is best to achieve a linear relationship to the analog input. However, this exceeds the capacity of the PIC. You may have to limit the table to 500 items and interpolate in-between values.
d. Enable interrupts for the CCP1 by setting CCP1IE bit in PIE1 register. When everthing is all setup, enable interrupts by setting GIE and PEIE in the INTCON register.

The following is a sample interrupt service routine:

Code:

;=======================================
         ORG      4

INT_SERVE:                             ; 2
         MOVWF    TEMP_W
         SWAPF    STATUS,W
         CLRF     STATUS         ; Select RAM BANK0
         MOVWF    TEMP_S
         MOVF     PCLATH,W
         MOVWF    TPCLATH
         CLRF     PCLATH
;--------------------------------------------------
         BTFSC    SELECT_PIN
         INCF     PHASE_CNT,F
         BTFSS    SELECT_PIN
         DECF     PHASE_CNT,F
;
         CALL     GET_PHASE            ; 8
         MOVWF    PORTB
;--------------------------------------------------
UPD_TIMER:
         BTFSS    UPD_TMR_VAL
         GOTO     UPD_TIMER_END
         BCF      UPD_TMR_VAL
;
         MOVF     TMR_VAL,W
         MOVWF    CCPR1L
         MOVF     TMR_VAL+1,W
         MOVWF    CCPR1H
UPD_TIMER_END:
;--------------------------------------------------
INT_SERVE_END:
         BCF      PIR1,CCP1IF
;
         MOVF     TPCLATH,W
         MOVWF    PCLATH
         SWAPF    TEMP_S,W
         MOVWF    STATUS
         SWAPF    TEMP_W,F
         SWAPF    TEMP_W,W
;
         RETFIE                        ; 2
;=======================================
GET_PHASE:
         MOVF     PHASE_CNT,W
         ANDLW    B'00000011'
         ADDWF    PCL,F
         RETLW    B'00000101'
         RETLW    B'00001001'
         RETLW    B'00001010'
         RETLW    B'00000110'
;--------------------------------------------------

The ISR uses 38 instruction cycles or 7.6usec. At 50Khz interrupt rate, there are 100 or 20usec instruction steps between interrupts. This gives a utilization of 38% of CPU cycles for pulse generation.

Originally Posted by Andy_123

Just a quick update:
I was going over the program last night - I think it will do the job, I will modify interruput routie a little and add analog input readings.

I would recommend to add the analog input readings on the main program instead of the ISR. The interrupts occur at varying rate. The A/D conversion is completed asynchronous to this.

I would also recommend to average the analog readings over several samples to reduce the effect of noise. This is possible because you can make up to 50K samples/sec.

Let me answer the second question first.

- What is a max value in ccpr1l? 2^16-1= 65535?
If yes I will need to set only CCPR1L for all dividers leaving CCPR1H=0.
This will reduce a lookup table size from 2000 to 1000 values.

The maximum value is 65535. If CCPR1H is fixed at 0, the maximum value of the pair becomes 255. Therefore the minimum frequency is 2,500,000/255=9.8Khz. To generate 50Hz, you would need a value of 50,000 or CCPR1H=0C3h, CCPR1L=50h.

- Timer value updated only at the interrupt routine (ccpr1l, ccpr1h):
Can this be done in the main program?
I see the reaction time issue at the low speeds and at speed "0"

If you write to CCPR1 in the main program, an interrupt can occur while writing to one register only (partial update of CCPR1 registers). Writing within the interrupt service routine guarantees both registers can be updated before the next interrupt occurs.

I understand at low speed, it will take longer before CCPR1 is written. However, rapidly changing CCPR1 will not speed up the response because the value of CCPR1 is only used when a match with TMR1 occurs.

The frequency divider method works from 50Hz-50Khz speeds. At speed 0, the TMR1 can be turned OFF and turned back ON when the speed is non-zero. Even at 50Hz, the update time is 0.02sec which is faster than your requirement.

It takes 4 interrupts to generate a complete sequence, right?
With max interrupt rate of 50kHz we can generate only 12.5Khz stream not 50Khz.
If this is correct what will be the best way to correct it: change value in CCPR1?

If you change the prescale value of TMR1 from 1:2 to 1:1, you could double the speed. This will increase the CPU utilization to 80%. Quadrupling the frequency would push it beyond the PIC16F628's capability.

You may change to a PIC18F242. The speed of the chip is double that of the PIC16F628. In addition to the increased storage for the look-up table, it has the TABLRD instruction to allow reading of the entire 16-bit program memory word. Added to that, optimizations with context saving will reduce ISR service time and CPU utilization.