Originally Posted by brodin

I wounder how it works with the STATUS register on a PIC 16F877.

I am using adress 03h. And that works even if I am in Bank1, where i probably should use 83h instead.

There is no 'address 83h' as such, it's just a convention for the assembler (that replaces it with 03h). The actual address 83h is a GPR in bank zero.

Should i use the correct adress for each bank I am in or is it ok to allways use 03h?

STATUS (as clearly shown in the datasheet) is present in all banks, using 03h is fine, it's what the hardware uses, and it's what the assembler uses.

Originally Posted by brodin

I wounder how it works with the STATUS register on a PIC 16F877.

I am using adress 03h. And that works even if I am in Bank1, where i probably should use 83h instead.

Should i use the correct adress for each bank I am in or is it ok to allways use 03h?

The address of any register is stored inside each instruction as 7-bit. Therefore, it makes no difference if you use 03H or 83H to access STATUS. They all become 03H when the highest bit is dropped.

Similarily, even if you use 85H, you are still accessing PORT A if you are in bank0. Or, 05H would allow you to access TRISA if you are in bank1.

The full address only matters when one uses indirect addressing where all 8 bits address is being used. So using indirect addressing, one can use 05H to access PORT A and 85H to access TRISA.

[quote="eblc1388"]

Originally Posted by brodin

The full address only matters when one uses indirect addressing where all 8 bits address is being used. So using indirect addressing, one can use 05H to access PORT A and 85H to access TRISA.

How would that work when 85h is in GPR memory space?.

Originally Posted by Nigel Goodwin

How would that work when 85h is in GPR memory space?.

No. For 16F877, address 85H is TRISA and it is not inside the GPR ranges.

Originally Posted by eblc1388

Originally Posted by Nigel Goodwin

How would that work when 85h is in GPR memory space?.

No. For 16F877, address 85H is TRISA and it is not inside the GPR ranges.

Sorry, yes, bank zero ends at 07Fh.

Have you actually tried it though?, and does it work?, and (probably more importantly?) why would you want to?.

Originally Posted by Nigel Goodwin

Have you actually tried it though?, and does it work?,

It has to work. It just indirect addressing via FSR.

Originally Posted by Nigel Goodwin

and (probably more importantly?) why would you want to?.

It allows the programmer to have full control on registers in both banks at once without the need to change bank bits in STATUS.

For example, one can have full software control to PORT A via direct addressing and TRISA via indirect addressing.

Originally Posted by eblc1388

Originally Posted by Nigel Goodwin

Have you actually tried it though?, and does it work?,

It has to work. It just indirect addressing via FSR.

You're assuming they are actually at that physical address?, but (from what you've said) you don't actually know it, and have never tried it?.

Originally Posted by Nigel Goodwin

You're assuming they are actually at that physical address?, but (from what you've said) you don't actually know it, and have never tried it?.

The Microchip datasheet tells me that they are there at that physical addresses.

You consider the datasheet wrong in this respect?

Originally Posted by eblc1388

Originally Posted by Nigel Goodwin

You're assuming they are actually at that physical address?, but (from what you've said) you don't actually know it, and have never tried it?.

The Microchip datasheet tells me that they are there at that physical addresses.

You consider the datasheet wrong in this respect?

Who knows?, the assembler doesn't consider them at that address 8)

Originally Posted by Nigel Goodwin

Who knows?, the assembler doesn't consider them at that address 8)

You should really update your assembler to the current version.

The following is part of the 16F877.inc file from Microchip. Can you tell what address is TRISA or TRISB?

Code:

;==========================================================================
;
;       Verify Processor
;
;==========================================================================

        IFNDEF __16F877
           MESSG "Processor-header file mismatch.  Verify selected processor."
        ENDIF

;==========================================================================
;
;       Register Definitions
;
;==========================================================================

W                            EQU     H'0000'
F                            EQU     H'0001'

;----- Register Files------------------------------------------------------

INDF                         EQU     H'0000'
TMR0                         EQU     H'0001'
PCL                          EQU     H'0002'
STATUS                       EQU     H'0003'
FSR                          EQU     H'0004'
PORTA                        EQU     H'0005'
PORTB                        EQU     H'0006'
PORTC                        EQU     H'0007'
PORTD                        EQU     H'0008'
PORTE                        EQU     H'0009'
PCLATH                       EQU     H'000A'
INTCON                       EQU     H'000B'
PIR1                         EQU     H'000C'
PIR2                         EQU     H'000D'
TMR1L                        EQU     H'000E'
TMR1H                        EQU     H'000F'
T1CON                        EQU     H'0010'
TMR2                         EQU     H'0011'
T2CON                        EQU     H'0012'
SSPBUF                       EQU     H'0013'
SSPCON                       EQU     H'0014'
CCPR1L                       EQU     H'0015'
CCPR1H                       EQU     H'0016'
CCP1CON                      EQU     H'0017'
RCSTA                        EQU     H'0018'
TXREG                        EQU     H'0019'
RCREG                        EQU     H'001A'
CCPR2L                       EQU     H'001B'
CCPR2H                       EQU     H'001C'
CCP2CON                      EQU     H'001D'
ADRESH                       EQU     H'001E'
ADCON0                       EQU     H'001F'

OPTION_REG                   EQU     H'0081'
TRISA                        EQU     H'0085'
TRISB                        EQU     H'0086'
TRISC                        EQU     H'0087'
TRISD                        EQU     H'0088'
TRISE                        EQU     H'0089'
PIE1                         EQU     H'008C'
PIE2                         EQU     H'008D'
PCON                         EQU     H'008E'
SSPCON2                      EQU     H'0091'
PR2                          EQU     H'0092'
SSPADD                       EQU     H'0093'
SSPSTAT                      EQU     H'0094'
TXSTA                        EQU     H'0098'
SPBRG                        EQU     H'0099'
ADRESL                       EQU     H'009E'
ADCON1                       EQU     H'009F'

Originally Posted by eblc1388

Originally Posted by Nigel Goodwin

Who knows?, the assembler doesn't consider them at that address 8)

You should really update your assembler to the current version.

The following is part of the 16F877.inc file from Microchip. Can you tell what address is TRISA or TRISB?

But that's NOT what it produces!, it produces 05 and 06 for TrisA and TrisB.

Originally Posted by Nigel Goodwin

But that's NOT what it produces!, it produces 05 and 06 for TrisA and TrisB.

The result is dropping of the eighth bit so 85H==05H if the eighth bit is dropped.

In fact, I should really say only seven of the address bits is being used as for example EECON1 has the address 18CH and is nine bit wide. So its address will assembled to 0CH.

As I said earlier, the eighth or higher bit in an address used for direct addressing is dropped by the assembler because the instruction has only the space of seven bits for address. In this case, the bank bits must be correct in order to access TRISA using 05H as an address.

Now consider the following code, with the IRP bit=0:

Code:

movlw   TRISA   ;W will contains 85H, not 05H
movwf   FSR     ;FSR now contains 85H
movlw   H'FF'   ;W now contains 'FF'
movwf   INDF    ;all port A pins are now set as inputs

The above code will not work if TRISA has the address 05H, because 05H is the address of PORT A, not TRISA. So the assembler only cut off the eighth bit during direct addressing, but use all 8bits for indirect addressing.

Safe, but not quite. It drops the nineth bit during indirect addressing(EECON1 address becomes 8CH instead of 18CH) so the IRP bit must be correct in indirect addressing to access the EECON1.

eblc1388 is right. We can see that FSR will take an 8 bit address. This picture should make it clear:

Looks like Jay has found the definitive graphic?.