Oznog

I've got a system using 7-bit addressed I2C comm between a PIC18F452 and a PIC18F252 using the SSP module. It has been in operation with the Master doing all reads from the Slave. I now need to do a few writes to the Slave so I added code to Master & Slave to handle them.

So far I got the Master to continue its reads and writes error-free as far as I can see, but the Slave code for the first write byte and the code for the following writes is just not getting hit. I don't have detailed info on what the slave sees, but these get logged into data for the next read and it's just not getting hit.

I looked at my existing read code and I put a "1" as the LSB in SPADDR reg. I'm not sure if this constituted the "R/W" bit- the R/W bit on the port needs to be 0- but if I recall correctly when I set it to 0 for writes then the Master got hung up waiting for the Slave response. I looked through the Microchip spec several times and couldn't figure out what the extra bit in the SPADDR reg does when you've only got a 7-bit addr.

Any obvious errors you can think of before I try posting a lot of code?

williB

i looked at the data sheet for the 452 ..
i could not find the SPADDR reg you speak of..

Oznog

SSPADD.