I have a combinatoric circuit that will reset a stage (one of several sr-flipflops).


Then I discovered that if both A (set-button) and B (from reset button) goes high at same time (like if they're wired together) that will cause S to go high for some ns and then go because of delay in leftmost and gate.

Then I start working boolean algebra, but I won't get any similar circuit that won't producing spikes when A and B shift state same time.

Also I would like trying avoiding any aditional delay circuits that hasn't other purposes than only delay the signal.

Any ideas?

Add a buffer of the same type as the other gates on the 'A' input to the second gate. This will add a delay so both signals reach the second gate at the same time, minimising the delay between them.

Its a compromise between speed and hazard elimination. The sequential circuit would produce a longer delay but eliminate the hazards.

Are you using the fastest logic family because if you use fast logic the delay will be minimised. The fastest i believe is 74G**.

Originally Posted by Jules_Theone

Its a compromise between speed and hazard elimination. The sequential circuit would produce a longer delay but eliminate the hazards.

Are you using the fastest logic family because if you use fast logic the delay will be minimised. The fastest i believe is 74G**.

At this moment, this is only a theoretical question, so the physical component isn't chosed yet. But I presuppose that all logic gates in the circuit provide roughly the same delay time.

But sure I get a very fast nand gate (the left one) and put in a slower one for the right. But then again, I probably have to spend more physical IC's on a board than neccesary just to provide a longer delay.
I think instead I can use two inverters in serie of same type (ttl-family) as the two and gates.

Try to see the propagation delay of each gates (semicondutors produces interal delays).

True, but sometimes its an issue if you're working at highspeed specially if the timing is critical

and the poster mentioned, causes S to go high for some ns and then go because of delay in leftmost and gate.

Initially, the inputs are lo. the complementary input of the right most gate is actually hi. at the switch turned to hi, because of the propagation delay of some ns of the left most gate, the complementary input is still hi for some ns while A changes to hi. so the output S stays hi for some ns. when the input of the left most gate propagates to the output, the complementary input becomes lo and thus, S becomes lo until the change of status.