So apparently during power up the MCU can't be depended on to react quickly enough to take control of the MOS gates and they may misbehave. So it's recommended to put some pull-down resistors (or pull-up if PMOS) on the NMOS gates to keep the in a known state in the absence of everything else.

The possible problem is that the NMOS are being powered from a boostrap circuit and the presence of a pull-down resistor at any value makes the charge in the boostrap cap not last nearly as long as it could since it is constantly leaking current.

Would it do the job to pull the gate driver inputs low instead? Obviously it would if the gate driver had power to it...but what if it doesn't power up in time? It would probably power up a lot faster than the MCU, or it might not (it's being powered from a boost converter that also needs time to set up). Either way, it still might not power on fast enough to propogate the control signal to the MOS gate in time since when the battery is connected, the voltage appears across the MOSFETs right away whereas the driver and it's boost converter need time to power up. Whereas directly pulling the gate low would have the gate always be in a known state even if no power was applied.

Or should I just make it simple and use a ridiculously high pull-down resistor directly on the gate (like 1M or 10M).

 

Or maybe I should just leave the high-side gates alone and only pull the low-side gates low. I mean...on power-up, who really cares what the MOSFETs do as long as they don't make a short? If the the low-side MOSFETs are ensured to be off, then who cares what the high-side ones do?

EDIT: Wait a second. Why would the high-side NMOS do anything? THe bootstrap caps aren't charged up on power-up.

 

I had a circuit like that. It used an opto-isolated PNP to control the gate and a 1K pull down on the gate to turn it off quick as well as stable start up. It worked fine.

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Thats recommended in order to save it from false triggering and has nothing to do with speed.

No, No dont put pull down resistor directly at the gate . There are Drivers which are designed for boot strap compatible operation .

Also have a look at here
http://focus.ti.com/lit/an/slua373/slua373.pdf

-Adi

 

Hmmm.... there should always be a resistor there since unpowered some chips will let it float.

It also depends on both the mosfet type and the voltage you are switching since the miller effect ( drain source capacitance pulling the gate as the supply voltage changes) will turn it on as well.

Dan

 

Wouldn't the driver prevent false triggering once it's powered up? I thought the resistor was there so that when the ICs were powering up, the gate would be a known state.

Did you misunderstand my question? One of my concerns was if I used a pull-down resistor on the high-side so that the gate would be in a known state as things were powering up, is that the same resistor would constantly be leaking current from the bootstrap capacitor which is not a good thing.

If I do have to use one on the high-side gates, I'm a bit curious as to what value I should use. Because 100M would give me the same leakage as the MOSFET gate-source leakage, but it might also be too big to do anything useful. A 1K (or even 50K is out of the question because the leakage is FAR FAR too great to allow the boostrap cap to keep the FET on for long a sufficient period of time.). THe value is less important on the low-side gates since I have an "infinite" supply of charge to leak through the resistor.

Currently, I have the low-side gates pulled-down unless someone can give me a reason as to why I should do the same thing for the gates (like false triggering, but I don't see how that happens when the drivers are powered up). My theory right now is there are no boostrap capacitors to leak on the low-side gates and if they are all off on startup before the ICs can take control of the gates...who cares what the high-side ones do since it will never cause a shoot-through condition.

THe driver I am using has internal pull-downs on both inputs, but not on the outputs. So in the absence of an MCU it will output a known state...but obviously, I'm more concerned with the output of the gate driver when it is unpowered or semi-powered.

 

What driver IC are you using? Is this a constant switching frequency/PWM app? Full bridge or half bridge?

If full bridge, just pull the gates low on the low side fets and ignore the high side. Where I used to work 10K was a common value for a gate pull down resistor.

 

I am using three IRS2186 half bridge drivers, one for each phase. Any two behave like a H-bridge at any one time (BLDC). It is PWM, but I'm not sure if I want constant frequency yet. I may use variable frequency for when the motor is spinning more slowly reduce losses (sensorless scheme's sampling is based on PWM frequency.)

 

Time to use your CRO dknguyen.

-Adi

 

What's a CRO?

EDIT: Oh, an oscope.

 

Hi,


If i followed your notes then perhaps you can use a time period
solution that is known to work with all time but cant be employed
for all time because it isnt appropriate for some time periods.

That is, take (for example) two 10k resistors and use them as
pull downs, but dont connect them directly to ground but instead
to the collector of an NPN transistor (emitter to ground). When the
transistor is on, the gates are pulled down close to ground, and when
the transistor is off, only the collector leakage current flows.
The only task left then is to figure out a way to generate a timing
pulse to the base of the NPN. Perhaps with charging cap (+Vcc to
base plus series resistor) so that at the instant of turn on all the
gates get pulled down, but that only lasts until the cap charges.
Ditto with a MOSFET for the controlling device instead of NPN.
The MOSFET would even be faster, and gate timing could be
made such that the pull down circuit pulls down faster than any
gate can turn on.

Another approach might be to use a dedicated uC pin, delaying its
effect with a capacitor so that it has to hover at some stable
logic level in order to charge the cap, and charging the cap
turns off the pull downs with appropriate transistor circuit.

 

Actually on a cpu pin you want one to keep the gate discharged. A passing magnetic field is enough to generate charges on the board and static is enough to turn it on or blow it out.

Dan

 

This is supposed to go on a very small plane so I don't have room for additional transistors.


Hmmmm. You are referring to the power-off condition right? Because when power is on the gate driver should be holding the gates in a certain state. Unless you are also referring to a passing field or shock charging up the capacitor to higher than the gate voltage limits.

 

yep, you were talking about a startup issue. the driver need some minimum voltage before it can take control. until then a passing field or static hit can disturb things

Dan

 

hi MrAI,
i am new to electro-tech..
could you explain how to use a MOSFET in the pull-down circuitry which stays open after power up and connects the pull-down resistor to ground when the gate driver is powered down.
could you tell how to generate the time pulse that you were talking about?