Help me out with this "fully turned on" business of FET's, as I came across this the other day. What indicates a fully turned on condition? I haven't done much in the way of power systems.

 

MOSFETs have a linear region and a saturation region (see graph). Once they reach their saturation region, they're fully on.

See also:
MOSFET - Wikipedia, the free encyclopedia
High Voltage Switches (Slideshow with sound)
SMPS Power Switch (Slideshow with sound)

Attached Thumbnails

 

Attached Files

NFET BSS138.pdf (121.1 KB, 21 views)

 

Hmmm.... yesterday we were discussing driving an IRF7201 in triode mode to drive a relay coil, and the subject of "fully on" came up. I need help choosing a transistor I think AG is very knowledgable about these things, and knows what he's talking about, as do you. But I still can't get my head around the concept. BTW, I looked at the Rdson spec for the 7201, and it was specified for both VG=10V and VG=4.5V. Below 20A Drain current, Rdson was around .05Π I think for both inputs. But over ID=20A, there was significant difference. So, I assumed that was the difference between being "fully" on and just "on."

Anyway, there seems to be many ways to define what "on" is. I just need to understand the vocabulary.

 

If you look at the IRF7201 datasheet again, you'll notice the Rds(on) at 10V == 30mΩ, and 4.5V == 50mΩ.

Being "fully on" just means that you have hit the top(or bottom) side of the Rds(on) curve. That the resistance is about as low as it's going to go, regardless of how much more voltage you apply to the gate. There is no real set point at which this happens, and more of an acceptable point to the application at hand.

The DS shows the gate threshold voltage to be only 1V. That's when the MOSFET starts to turn on and pass current, but at a very high resistance. It's not until the gate hits ~4V that the resistance finally starts hitting an acceptable range.

Figure 6 of the DS is showing that using only 4.5V at the gate will hit a maximum saturation of the drain-source junction due to the field not being large enough for the entire channel to conduct. It's not "fully on" yet for that amount of current. If you wanted to pass more current, you would have to drive it with a higher gate voltage.

 

Actually, I'm looking at an International Rectifier IRF7201 datasheet, and it appears that around Id=5A, Rds~=.025 @ 10V and ~=.035 @ 4.5V. That seems like such a small difference. However, as Id reaches around 20A, the curve for Vg=4.5V appears to spike up exponentially, while the 10V curve remains flat. IRF7201 pdf, IRF7201 description, IRF7201 datasheets, IRF7201 view ::: ALLDATASHEET :::

Would it be corret to say that under 20A, the device is "fully on" with VG=4.5V, but not at Id>20A?

 

It's a 40% increase in resistance, which means a 40% increase in power dissipation. Might seem small, but it's all about percentages here.

Correct. Drain-source current does have an affect on the channel resistance. Although I don't know the exact details as to why. Yet.

 

Ok, by "small" I mean in comparison to the load. If the supplies were, say 30V, and Id was 5A, then the total circuit resistance is 6 Ohms. So going from 6 Ohms to 5.99 Ohms is pretty insignificant to the circuit operation, and 175mW vs 125Mw isn't usually going to be much of a concern, unless you're on a really limited energy source.

But anyway, thanks! I think I'm getting there.

Edit: "Thanks!

 

Hi there,


" 'Fully On' is in the meter of the beholder" :-)

What is more important is the answer to this question:
"Does the device turn on enough for my application or not?".

If the answer is 'yes', you are good to go. If not, better look for
another device or a better way of turning it on.
Keep in mind that some devices turn on with roughly 4 ohms min,
while others turn on with say 0.040 ohms min. What works for
your application works, and what doesnt, well, doesnt.

1. Review the data sheet
2. Review the application design
3. Make the go/no go decision
4. You're done.

 

The MOSFET will be "on" whenever Vgs exceeds Vt. Once this occurs, the channel between the source and the drain is created. As Vgs is increased, the channel becomes "wider" and thus the impedance between the drain and the source decreases.

Now keep Vgs constant and start increasing Vds. The channel near the drain starts getting narrower and narrower until Vds = Vgs - Vt. At this point, the channel shape will remain the same which limits the current regardless of Vds. So the enhancement channel is affected by Vds which can limit the amount of current through the FET. So if Vds keeps increasing but the current remains the same, that, in effect, translates to an increasing impedance.

In a switching application you really don't want to put the FET in the saturation region. You want the Rds(on) to be predictable and you want the losses to be low. That means a low voltage across the drain to source and as low an Rds(on) as you can get. Basically a switchable resistor.

If you are operating the FET in the saturation region, you'll really need to watch the power dissipation - unless the duration is short or you have some really good cooling to keep the junction temp down, the FET will likely burn up.