Boncuk

Hi Blueteeth,

thank you very much for your kind offer. Let me download the data sheet of the MACH4. It is no problem to purchase a single device in Germany. It costs EURO 5.80 incl. sales tax. The minimum order there is EURO 10.00. No problem at all. Might be interesting for you too. 24 hour delivery service at lowest possible shipment cost: Reichelt Elektronik - OnlineShop für PC-Komponenten, Elektronik - Festplatten, Mainboards, Motherboards, Karten, Kabel.

If you habe problems ordering there I would be happy to help you. I've been working with Reichelt for more than 40 years and their service is perfect - much better than Conrad.

In that matter you might as well forget about Thailand. You can buy all kinds of industrial overproduction parts and all kind of junk here, but never a specific part.

I received your email OK. I guess OAL just sends you a reply that the mail has landed.

Greetings

Hans

petrv

Hi Hans,
the code for the PLD is in ABEL. Unfortunately I don't use ABEL, only VHDL - actually this is the first ABEL code I have seen. I have checked the Xilinx tutorial on ABEL and according to that I got some understanding of the code (It seems to me that ABEL is much more primitive and low-level language than VHDL). I rewrote (yesterday) the logic in VHDL and ran synthesis for XC9536 - was ok with about 53% usage of the CPLD resources and I have got a programming file.

It is not the best design (one of the rules of a good PLD design is to run all flip flops from a single clock and "gated" clocks are not a good idea) but it should work for your application.

Boncuk

Hi petrv,

I don't know exactly what the "gated" clock is good for, but I imagine the clock frequency of 12.8MHz is divided by some factor to match the ATMEL CPUs requirements. The clock signal for the CPLD is supplied directly by a XTAL-oscillator circuit.

I also don't know about ABEL or VHDL. I just want to build that frequency counter, of which I think it's worth building it, just because using the proper prescaler it is able to work up to 2.4GHz with an eight-digit display

It's also a matter of calculation. A frequency counter off the shelf with these properties will cost me about 300 EURO. The few parts required to build it will not cost more than 100 EURO. And after all - it's self made which I like.

Thank you so much your work. May be I try to build two samples, one using a Lattice device and the other one with a Xilinx CPLD.

Hans

petrv

Hi Hans,

Gated clock and its problems:

I assume you are familiar with TTL logic ICs like 7408,7474,7493,74161 ... (no matter what technology - LS, HC, HCT, AC, LVC ...)

Suppose you have a D flip-flop (like one half of 7474) and you need to update the output at the rising edge of a system clock but only when a certain condition (e.g. signal COND is true).

Normally the D flip flop will copy the logic level at its input D to its output Q at each rising edge of the clock CLK. One idea how to implement the condition is to add a combinatorial logic like for example an AND gate (7408) with inputs connected to the clock CLK and the condition signal COND. the output will go to the CLK pin of the D flip-flop. This is what is called a "gated clock" and it is not a very good design for several reasons. A good design is to connect all CLK input to all flip-flop and connect them to the same global clock signal (programmable logic devices are specifically optimized for such kind of design).

Of course if you connect the CLK without the gate the flip-flop will be updated every rising edge (unconditionally) but you can still implement the required functionality in another way - add a multiplexor (like 1/4 of 74157) to the D input of the flip-flop
and connect one input (A) of the MUX to the signal that was connected to the D gate and the other input (B) to the output Q of the flip flop. the condition will go to the mux switch (A/B). That means the condition will select which input of the MUX will be loaded into the flip flop. if it is the (A) input the FF will be updated normally,
if it is the (B) the D of the FF is connected in effect to Q so it is updated with its previous value which will seem like no update.

This is for example the difference between asynchronous (ripple) counters like 7493 and synchronous like 74161 or 74193. The synchronous counter has all CLK inputs of all its flip-flops connected together so all outputs are updated synchronously. But with asynchronous design some flip-flops are updated later as the clock is delayed and there are moments when some of the outputs are already updated and others not yet.

Luckily for you your CPLD design will run only on a low 12.8 MHz clock so these problem will not be significant but the Xilinx CPLD can run on clock higher than 100 MHz (the 3.3V XL family is even faster) and then this issues can be a real problem.

Petr

the other

Hero999

I know that you probably know this and I hate to be picky but half of those technologies aren't actually TTL but CMOS.

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petrv

Of course I know that but in this case it is a completely irrelevant detail. As I said the technology (be it LSTTL or advanced CMOS) is not important for understanding the principle of synchronous design, on the contrary, too many not relevant details can distract from the subject

Petr

Blueteeth

I've skimmed over the abel file (my native HDL language) and it looks fine to me.
Yes, maybe some bad practice with the 'gated clocks', but that only serves to limit its maximum operating frequency. So unless the user is planning to run the thing at Fmax (160-250Mhz) I doubt there will be any issues.

Saying that, if it doesn't work for you Boncuk, I could try and re-write the code to make sure everything is synchronous. But seeing as its a frequency counter...we run the risk of getting out of sync and introducing errors in the reading of the input. Lets see how it goes.

Blueteeth

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Boncuk

Hi petrv,

here is the Xilinx parallel port adapter. I wrote some comments into the schematic. Please check.

I also added a low current LED to indicate the presence of VCC. If you think it's unnecessary please let me know. Kicking off a part is no problem.

Hans

Attached Files

XILINX.zip (17.2 KB, 2 views)

petrv

Nice, but I have already designed one. Have you built the adapter ?