Blueteeth

I'd be happy to program a chip for you, be it lattice or Xilinx, but as petrv pointed out, simple PCI parallel port card + the parts for download cable (either a lattice OR a xilinx one) would just be less hassle for all concerned (especially your friend if he lives miles away from me ^^ ).

A few caveats for the download cable construction:
1) If your CPLD (again, xilinx or Lattice) is a 5v device, then thats fine, any form of TTL buffer would do. But if its a 3.3v device, many CPLD's require ISP downloading at their native VCC. Then agian, almost ALL 3.3v CPLD's are 5v tolerant, so you would just have to make sure you have a 3.3v power supply. As I said, if its 5v don't worry about it.

2) Some download cables connect two parallel port lines together as sort of loopback so the software recognises thats its plugged in...whether a device is connected to it or not. Don't forget it (my one cost me 5 hours of debugging).

Lets us know how you get on. And if you're looking for CPLD's, try ebay..I've recently just bought up about 30 different types, along with FPGA's, very cheap. total must be <100USD. Also...some even come with the dlownload cable pre-built still at ridiculous prices.

Blueteeth

__________________
Inconsistency is the key to flexibility!

Boncuk

Hi Blueteeth,

making a parallel cable should not be a problem. I suppose the loop backs are pins 8,11 and 12 for the Xilinx devices and pins 8,12 and 13 for the Lattice devices. (Pin numbers of the Sub-D25 male connector) The Lattice cable is not clear at all. It uses a 74HC244 and the logical symbols differ a lot from those in the data sheet. Additionally there are no pin numbers of the IC (HC244) contained in the schematic.

Is it correct to use only pins 20 and 25 of the Sub-25 connector for ground? Normally they are 18 through 25.

What worries me most is the fact, that there are pin describtions of the JTAG and power pins in the data sheet of the XC9536, but none for the I/O numbers. The programming software certainly doesn't know what is connected to which pin in the application. How did you find out the pin numbers and the I/O associated with them? (Try and fry? )

I guess, Chris needs a weekend trip from time to time. I'm not worried about that if I need his help.

If you happen to have a better schematic of the Lattice Port Adapter please foreward that to me.

Thank you very much for your help.

Regards

Hans

petrv

The Xilinx adapter is powered from the target circuit so it always outputs correct voltage levels on the JTAG pins, be it 5V or 3.3V - the 74HC125 can accept any voltage in the range 2V to 6V as power (Vcc). The Xilinx XC95..XL 3.3V family has 5V tolerant I/O and the devices are cheaper than th 5V XC95... family (but you will need a 3.3V regulator to power the CPLD).

I/O pin assignment - this is done when building the programming file using an .ucf file (User Constraint file). If you don't specify this file it will use whatever pins are the most convenient when the ISE Webpack creates the implementation but if you have designed the PCB with specific I/O pins going to be used for specific pins of your design, you must use the .ucf file to give location constraints. For example you can specify that input pin DATA1 of your design goes to pin 33 of your physical CPLD package.

Boncuk

Hi petrv,

thank you for the information. However it is getting confusing more and more.

I attached a fraction of the schematic with all pins labelled. The output pins of the AT90S8515 are all used for the 8-digit LED display.

If you have the time would you kindly make a "translation" from Lattice to Xilinx pin numbers?

Regards

Hans

petrv

Hi,

do you have the understanding of the function the PLD is supposed to perform ?
This is essential for you to succeed, otherwise you can't do it, the same as you cannot for example replace a microcontroller in a design with a different type (e.g PIC with AVR or the other way) if you have no idea what is the software inside doing ... same with the PLD. Could you define the function - e.g. as a schematic using TTL logic ? Or a good description what it does ?
If yes then it is the time to start the Webpack (I hope you downloaded and installed it already) and start the new design wizard ... The I/O pin assignment is just a small thing but you need first to design the logic that goes into that CPLD.

Petr

Blueteeth

As petrv mentioned....the pins a cpld use is entirely down to the user. If you have a design that uses only 5 I/O's....then you can use any I/O for any of them (except obviously the JTAG and power/gnd pins). This is indeed 'confusing' if you don't have the source code. As a jeduc/hex file for the CPLD will already have this information. In which case you'll have to use the original device and it can then be used exactly as in the schematic (its I/O's are already assigned).

A translation from lattice to xilinx part numbers is sort of down to you This is why sometimes it isn't best to change horses.

If you have the VHDL/verilog/schematic source, then as petrv suggested, xilinx ISE webpack will happily take this, then you map the I/O's (in the design each input/output wil have a name, just tell the software what names go to what pins). Set the device, and program. I will pm you my email address, and if you want, email me the source/url or the project.


Right now I see we've got several problems that need to be solved:

1. Decide whether you can get the lattice CPLD in question (2032), or whether it is easier for you to aquire a xilinx equivilent (part numbers already mentioned).

2. IF you have the code/schematic (for programming the CPLD) then you can use either lattice OR xilinx parts. If you only have tghe jedec file, you're pretty much stuck with having to use the Lattice 2032.

2a. As another option (not an easy one). If you know exactly what the CPLD is supposed to do, then I suppose I could attempt to write some VHDL or create a CPLD schematic and send it to you, so you can use it for XIlinx OR Lattice parts.

3. Download cable. As you seem happy to get a PCI parallel port card, then its just a case of getting decent schematics for the cable. Again, xilinx or Lattice? Xilinx have some easy-to-read schems, but as you rightly pointed out, the schem for the lattice cable is a bit of bugger. I shall reverse engineer my DIY download cable (works with every lattice part I got) and provide a Eagle schem, parts list, and if you REALLY want, a stripboard layout. Or even if you are willing to make a PCB for it (works jsut fine on stripboard) I may even be nice enough to design a custom PCB

So, there are all the options. It is indeed confusing, took me ages to get the hang of using CPLD's but once you get it, its pretty cool, and extremely handy.

As I said, I shall send you a personal message in this board with my email address. Send me all the info you have on the project. If its on a webpage, then a url would be fine...if you have source codes, send them. Obviously I won't really need the microcontroller code, its all about that Lattice thing.

Good luck, we'll get there eventually mate.

Blueteeth

__________________
Inconsistency is the key to flexibility!

petrv

Hi,
in addition to my previous post, you can read my tutorial on programming CPLDs.

Regarding the schematics you have posted - I need to see the complete schematics, this part is too small to understand it enough. If all that you need is a prescaler it should not be that hard to implement in VHDL but I still don't have enough information about the project to give you more specific advice.

Boncuk

Hi petrv,

I know that I can use any pin of a CPLD for I/O, except for the reserved (programming) pins.

The file I already mentioned (word document) seems to be a UC file. There are exact pin describtions and functions contained in it.

Sorry, I couldn't download any software until now. First, Thailand has a big problems concerning internet band width. A file of more than 600MB size takes about 24 hours to download. Second, even if I start download the electric power supply will fail for sure within those 24 hours. Using a UPS (which I do) won't make much difference if the power failure lasts more than 30 minutes.

I also read your tutorial. For this time I think it will be better to stick with Lattice.

I sent the complete schematic and every information to it already to blueteeth. If you are interested you might take a look at the file and find out if it is good enough to program the chip.

Thanks to both of you for your kindness and patience with a man who starts grasping things slower.

Regards

Hans


Sorry, upload won't work. Friday evening - Thailand is playing.

Blueteeth

Yeah, the software for CPLD's/FPGAs, be it lattice or xilinx is ridiculous. 400-700MB. Shocker.

You're welcome. I had a slow start to programmable logic, I guess its complicated because of the nature of CPLD's (completely reconfigurable in every way) but we'll get there.

And to petrv, good too see someone else is up on PLD's, you've proved invaluable in this thread, and to this forum. Keep it up

Blueteeth.

No rush on the files, whenever your internet decides to work. Annoying isn't it?

__________________
Inconsistency is the key to flexibility!

Boncuk

It's not only Lattice and Xilinx. Look at ATMEL's AVR-Studio. It's about the same. Programmers tend to become sloppy knowing there is a lot of memory to work with, other than working with 61KB of RAM space using C/PM some time ago.

The problem in Thailand is selfmade. Thailand supplies every neighbor country, Cambodia, Laos, Birma (Myanmar) and Malaysia with internet service, including the servers. Those countries don't have own internet servers. Using steam driven servers they won't do much of band width.

I tried internet via an analog modem before. The amazing download speed was 50bits/second.

Hans

blueroomelectronics

I had to repair my notebook recently, the power connector came loose from stress. Anyway I pulled the analog modem out while I had it apart. Never used the thing and all it did was chew away at the batteries and as it was a software modem it was just one less driver to worry about.

__________________
Bill
Smart Kits build Smart People
http://www.blueroomelectronics.com

Boncuk

Hi petrv,

I hope the upload will work this time.

petrv

So where is your upload ? BTW regarding the Xilinx Webpack download they do have a download manager so you can resume interrupted downloads if there was a problem with your internet connection. Still I guess I am lucky having access to 5-Mbit ADSL connection I have just upgraded the Webpack from 9.1 to 10.1 and the download size has doubled (was over 1 GB now over 2 GB) And then also the service pack and IP upgrade pack ...
But all downloaded and installed it works very well.

Another possibility is to order the webpack installation DVD for a small fee from Xilinx.
I have got a DVD with the ISE Webpack when I bought the Spartan 3E starter kit from Xilinx 2 years ago ... (one of my 3 FPGA boards, other two are from XESS homepage announcements)

FPGAs programmed in almost the same way as CPLDs but they are much more powerful.
For example I have implemented the ZX Spectrum 48k 8-bit computer as a SoC all inside one FPGA ...

When you start using PLDs and especially FPGAs you'll discover how much hey are powerful.

Petr

Boncuk

I would certainly like to upload a file. According to Nigel Goodwin's information there was an aparent upgrade of the software at electro-tech-online. I tend to believe it was a downgrade - no possibity for attachments.

Good you have high speed. That's what Thais are dreaming of - me too.

Hans

Correction: Now the option is here again - done

Blueteeth

Hey,

I replied to your email, and sent my own lattice cable schem. But I got an automated response, so I sent it again ^^

And thinking about it, I have a few MACH4A5-32/32 's here, lattice, 32MC, pretty quick, similar pinout, same package (PLCC). If you like I could put that CPLD design into my software, load it into the chip, and send it. Just tell me what pins you would like each function to be.
Blueteeth

__________________
Inconsistency is the key to flexibility!