Hi,

Could someone please help me ?

I can't figure out how to use VIA's in Eagle.

I can't draw a signal from an IC pin to a VIA, It just will not work.
and If I try to use a wire it sayes there is a clearence problem on the DRC.

I've looked all over the internet, and reviewed several tutorails without
any luck.

I'm designing a Prototype board that has a large amount of VIA's
for a prototyping area.

Please help,
Thanks,
-Areal

 

For the prototype area vias with wires going to them. Create the signal and connect it to a one pin "pin header" on the schematic. You can place the pin in your grid of vias in the board editor.

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Not sure what you mean. Normally you would have the "layer picker" or whatever it is called set to "top" and then you click on the IC pin, then you make your way to your destination. When you want a via, you go to the layer picker and change to bottom and it will put a via there and you keep clicking until you reach the target. Am I missing something here? Maybe I did not understand your question.

 

If I understand the OP this is the type of thing you would not understand unless you have run into it.

He wants to do a breadboard area by using a lot of vias. He is placing the vias within the board editor. They do not exist in the schematic.

He wants to run traces from the existing circuit as defined by the schematic to these vias. Eagle will not let him do this. My solution was to use pin headers on the schematic in place of each via that connects to a signal The headers would not be populated. It is the via created by the header that we are after.

Did I get it right ?

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Yes, Thanks !

 

If you are designing a project you can share please do so

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Once you name the via the same as the trace that you have "connected" to it, the drc goes away.

Example, if you want to run a wire from VCC to a via, place the via and then change its name to VCC. You can then run the wire and it will connect properly.

 

Hi Areal,

I think you mean this (attachment). You can of course create vias by routing an air wire. There is one disadvantage to vias created that way. If for some reason you must ripup the trace the vias will disappear.

A better way is as follows: Create single pins as symbols. Save the pin and make a "package". This package will be a single solder pad. I suggest the diameter 0.063 inches and a drill size of 0.032 inches which matches IC pads.

Now comes the hard part of the work. You must place each single pin in the schematic. If you want to connect any signal to it you must also do it in the schematic.

That way I placed 915 "vias" on a PCB as an additional experimental area. You might ripup all signals, but none of those "vias" will disappear. There are being treated like any component in your schematic and PCB layout.

Hope this solves your problem.

Regards

Hans

 

Boncuk,
With you suggestion we now have three ways of doing the same thing. Funny thing is that I figured I nailed it the first time. Goes to show that there are often more then one way to do the same thing.

Mneary's solution works too. I was trying it and came up with this.

Place all the vias on the board (not schematic).
For the vias that will have signals name them the same as the signal, this will create air wires to the vias.
Route the signal to the vias.
If you choose to rip up the trace the air wires will remain.

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... with one disadvantage: Those vias are not "vacant" anymore, unless you don't route them. On the other hand, using just a few extra vias your method makes sense. Making a total of 915 for a wrap- or experimentation field you will very quickly run out of proper names for them. Eagle only accepts names already contained in the schematic. Using my method you really add "components", and it's up to you whether you connect them or not. (which has to be done in the schematic) Ignore the error messages "unconnected XX" which will appear in the ERC check.

Plan for one extra sheet per 300 pins.

Hans

P.S. That kind of work is something for somebody who has slain his mother and father.

 

I do not know what you mean by vacant?

In my last post I suggested placing all the prototype area vias directly on the board and not the schematic. Each time you name a via (on board) an airwire is created to it from a part with the same name. You only need to name the vias that have a connection to the circuits on the schematic.

Because you are putting these vias only on the board you can duplicate a row several times to rapidly create the full matrix.

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Hi 3v0,

by "not vacant" I mean that the named via belonging to a net can't be used for any other connection.

Placing any desired amount of vias on a PCB also means that there is no schematic loaded. Using this method you can certainly create masses of vias also by the copy and paste method.

If you load the schematic after the changes on the PCB are done the ERC will fail, and no more forward- backward annotation will be performed. Even changing a part with the same function and value, but different size, will not change both, schematic and PCB.

Without forward- backward annotation you will run into problems sooner or later. Finding a net error and correcting it after such a manipulation you must do it twice, once in the schematic and once on the PCB, which might result in multiple errors.

I must admit that my way to add "vias" is a bit much of work, but on the other hand you can connect any component to the "vias" in the schematic and changing to the PCB and performing a "rats nest" you'll immediately see the changes, and which is most important: They are error free!

BTW: You can also group "vias" in the schematic and paste with the advantage that they will have new numbers.

For clarification I have added a part of the schematic and the PCB. As you can see "via W340" is visible in the schematic and on the PCB. Clicking the connecting trace you will read PIO0.

 

We must be using a different program.
I did my testing use the beta version of Eagle 4.92.2 but I would think this is a basic behavior and not related to the beta.

The attached pdf is the board created from/with a schematic. Vias were added in the board editor. The vias with traces leading to them had the air wires created by naming the vias in the board editor. ERC and DRC report no errors.

I do not know why we are getting different results.

Attached Files

vias.pdf (9.4 KB, 7 views)

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What about defining the prototype area as an Eagle component (in a library) ?
Just create a package with a lot of pads (looking a bit like a PGA) - then you can easily place it on any board layout you need. And it won't disappear when ripping up traces.

Petr

 

You could do that. It would be easy enough. There are several ways to do the same thing. My suggestion is what seemed natural and easiest to me. I think everything said here will work, some are more labor intensive.

If you loose a via or two when you ripup a trace it is not a big deal. Drop another on the board and name it and the airwire comes back. If you have a lot of traces going to the prototype area run them to a pin header in the schematic. Treat the pinheader as if it were a via in the board editor.

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