Boncuk

Hi friends,

just a short question: I have paralleled six inputs and outputs of a CD40106 (inverting Schmitt-Trigger) for increased output power.

Eagle comes up with an error message when performing a DRC. "Six output pins on net M-CLK".

No error message concerning the paralleled input pins.

I will use this Master Clock signal for 10 or more decimal counters, so I suppose just one gate wouldn't be able to drive all.

Will there be a problem?

Boncuk

HS3

Maybe all the Schmit triggers will not trigger at the same time and that may cause problems. You might want to separate the outputs and give them each a manageable load.

BTW, a descriptive title is better than something which gives no idea what the thread is about.

mvs sarma

while hs3 may be correct, why should a Eagle software worry about it? whether it has spice built-in? I fear Boncuk , you may have to loop input pins pin to next, from next to further next and so on.and not all at the same time. Eagle will scrupulously follow the schematic. does not allow you other routing methods even though the result is same. .
thus in artwork if you prefer a particular pattern, is easy, please do modify the schematic accordingly.

__________________
Regards,
Sarma.

3v0

Sounds more like a ERC sort of thing. Eagle is just watching you back, I do not see a problem.

Do you need the schmidt trigger to clean up the signal. If not maybe use a transistor to drive the load ?

__________________
search engine for electronic parts
Junebug USB PIC programmer kit., USB Bit Wacker, Homepage
The 15 Minute Printed Circuit Board! (+drill time)

Boncuk

Hi HS3,

I think they will trigger simultaneously, just because they receive the same clock signal. The frequency is below 1KHz and they should be able to manage that. Since the circuit uses up to ten counters with the same clock I must take care that the signal is strong enough for all of them. The basic circuit just uses one counter. If desired more counters can be added. They all have to have the same clock signal for proper function.

Well, you are right. I'll think of that the next time. But the title made you curious though.

Boncuk

Boncuk

Hi 3v0,

indeed, it is an ERC. Just mistyping.

I put in a clean signal and I want a clean signal out. The idea using a transistor is very good. I didn't think of that possibility. Saves 9 pins and will be stronger than six gates, too. Thanks a lot for that input.

Eagle is sometimes a little bit strange. Use the autorouter with a grid of 0.3175mm (0.0125inches). Make a DRC and wonder how many errors appear. All "angle" errors. Put the max errors on 5.000. Eagle will stop after 50 errors if not raised properly.

Hans

Hero999

They should all trigger at exactly the same level because they are all on the same chip and therefore will be matched.

My guess it that Eagle is just paranoid because you shouldn't normally connect gate outputs directly together.

__________________
I also post at the following sites:
http://www.stop-microsoft.org http://www.heated-debates.com
Screen name: Aloone_Jonez

audioguru

If the counters are Cmos then they don't draw any input current. So with your slow clock frequency then one inverter should be able to clock at least 50 counters in parallel. Some brands of CD4017 counters have a Schmitt-trigger clock input.

__________________
Uncle $crooge

Boncuk

Thanks to all of you for your inputs.

Hi audioguru, looks fine except for "should" which leaves little doubt. I want to make the circuit work with no doubts involved for proper function. So just for that reason I will add either six paralleled Schmitt-Triggers ore one transistor.

I guess also CMOS-ICs are restricted in output power for a fan-out of about 10 although the single input won't have a high current load. Just a small phase shift makes the entire circuit work a way which is not intended.

Again, regard to All

Hans

kchriste

Audio is right, the fanout spec of 4000 series CMOS is much higher than 10. You're already driving the 6 inputs of your inverters anyway. Probably the bigger issue is if the wiring between the "Master clock" and the counters is long and has a lot of capacitance on it. Then using multiple gates will reduce the propagation delay time vs using a single gate. But I agree with Audio that the extra gates are probably not needed. To remove all doubt, put a scope on the clock line and measure the rise/fall times. Try it with and without the extra gates.

__________________
--- The days of the digital watch are numbered. ---

audioguru

The datasheet of the counter shows its input capacitance and its minimum clock rise time.
The datasheet of Texas Instruments Cmos logic ICs shows its minimum output current.
Put the two together to determine how many thousands of clock inputs one Cmos output can drive. Add a few pF for stray capacitance.

__________________
Uncle $crooge

Boncuk

Yes, I did. Nothing happened. Do you suggest to add uF?

audioguru

Nothing happened? A single Cmos gate did not clock 10 Cmos counters?
Which counter? What supply voltage?

Stray capacitance of a circuit is 20pF at the most. Not a few uF.

__________________
Uncle $crooge

Boncuk

Slight misunderstanding. Clocking was alright, but adding stray capacitance of a few pF nothing bad happened. It will certainly happen at higher frequencies of several hundred KHz. This circuit is well below 1KHz.

Counters are CD4017 and supply voltage is 9V.

audioguru

The CD4017 made by Texas Instruments has a Schmitt-trigger clock input. The CD4017 made by Fairchild and maybe others does not have the Schmitt-trigger input.

__________________
Uncle $crooge